From a66bdb19566b4c6ab33360c43adff9fe63a079b2 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 24 Sep 2015 17:53:26 -0700 Subject: [PATCH] replace remaining uses of Vec.fill --- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index f9650b95..65305f00 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -202,7 +202,7 @@ class ICache extends FrontendModule val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid) when (refill_done) { val tag = code.encode(s2_tag).toUInt - tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _)) + tag_array.write(s2_idx, Vec(nWays, tag), Vec.tabulate(nWays)(repl_way === _)) } val vb_array = Reg(init=Bits(0, nSets*nWays)) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index b7aff715..c4b246e9 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -669,7 +669,7 @@ class DataArray extends L1HellaCacheModule { for (p <- 0 until resp.size) { val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles) when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { - val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) + val data = Vec(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) array.write(waddr, data, wway_en.toBools) } resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits