From a6188efc412e2825b7d7d3993e4af84930d50185 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 18 Nov 2016 12:52:36 -0800 Subject: [PATCH] rocketchip: break infinite Config loops --- src/main/scala/coreplex/Configs.scala | 38 ++++++++++++------------- src/main/scala/groundtest/Configs.scala | 8 +++--- src/main/scala/rocketchip/Configs.scala | 12 ++++---- 3 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 4cffa127..a2ba04e2 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -122,19 +122,19 @@ class WithNCores(n: Int) extends Config( }) class WithNBanksPerMemChannel(n: Int) extends Config( - (pname, site, here) => pname match { - case BankedL2Config => site(BankedL2Config).copy(nBanksPerChannel = n) + (pname, site, here, up) => pname match { + case BankedL2Config => up(BankedL2Config).copy(nBanksPerChannel = n) }) class WithNTrackersPerBank(n: Int) extends Config( - (pname, site, here) => pname match { - case BroadcastConfig => site(BroadcastConfig).copy(nTrackers = n) + (pname, site, here, up) => pname match { + case BroadcastConfig => up(BroadcastConfig).copy(nTrackers = n) }) class WithDataScratchpad(n: Int) extends Config( - (pname,site,here) => pname match { + (pname,site,here,up) => pname match { case DataScratchpadSize => n - case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = n / site(CacheBlockBytes)) + case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = n / site(CacheBlockBytes)) case _ => throw new CDEMatchError }) @@ -152,8 +152,8 @@ class WithL2Cache extends Config( }) class WithBufferlessBroadcastHub extends Config( - (pname, site, here) => pname match { - case BroadcastConfig => site(BroadcastConfig).copy(bufferless = true) + (pname, site, here, up) => pname match { + case BroadcastConfig => up(BroadcastConfig).copy(bufferless = true) }) /** @@ -169,12 +169,12 @@ class WithBufferlessBroadcastHub extends Config( * DO NOT use this configuration. */ class WithStatelessBridge extends Config( - (pname,site,here) => pname match { - case BankedL2Config => site(BankedL2Config).copy(coherenceManager = { case (_, _) => + (pname,site,here,up) => pname match { + case BankedL2Config => up(BankedL2Config).copy(coherenceManager = { case (_, _) => val pass = LazyModule(new TLBuffer(0)) (pass.node, pass.node) }) - case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) + case DCacheKey => up(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError }) @@ -189,8 +189,8 @@ class WithL2Capacity(size_kb: Int) extends Config( }) class WithNL2Ways(n: Int) extends Config( - (pname,site,here) => pname match { - case CacheName("L2") => site(CacheName("L2")).copy(nWays = n) + (pname,site,here,up) => pname match { + case CacheName("L2") => up(CacheName("L2")).copy(nWays = n) }) class WithRV32 extends Config( @@ -201,21 +201,21 @@ class WithRV32 extends Config( }) class WithBlockingL1 extends Config( - (pname,site,here) => pname match { - case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) + (pname,site,here,up) => pname match { + case DCacheKey => up(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError }) class WithSmallCores extends Config( - (pname,site,here) => pname match { + (pname,site,here,up) => pname match { case MulDivKey => Some(MulDivConfig()) case FPUKey => None case UseVM => false case BtbKey => BtbParameters(nEntries = 0) case NAcquireTransactors => 2 - case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) - case CacheName("L1I") => site(CacheName("L1I")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) - case DCacheKey => site(DCacheKey).copy(nMSHRs = 0) + case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) + case CacheName("L1I") => up(CacheName("L1I")).copy(nSets = 64, nWays = 1, nTLBEntries = 4) + case DCacheKey => up(DCacheKey).copy(nMSHRs = 0) case _ => throw new CDEMatchError }) diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index e08a6976..d9c5d0f5 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -121,8 +121,8 @@ class WithAtomics extends Config( }) class WithPrefetches extends Config( - (pname, site, here) => pname match { - case ComparatorKey => site(ComparatorKey).copy(prefetches = true) + (pname, site, here, up) => pname match { + case ComparatorKey => up(ComparatorKey).copy(prefetches = true) case _ => throw new CDEMatchError }) @@ -182,7 +182,7 @@ class WithCacheRegressionTest extends Config( }) class WithTraceGen extends Config( - (pname, site, here) => pname match { + (pname, site, here, up) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 1, cached = 1) } @@ -201,6 +201,6 @@ class WithTraceGen extends Config( }.flatten } case UseAtomics => true - case CacheName("L1D") => site(CacheName("L1D")).copy(nSets = 16, nWays = 1) + case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 16, nWays = 1) case _ => throw new CDEMatchError }) diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala index b98af3db..93b8e7af 100644 --- a/src/main/scala/rocketchip/Configs.scala +++ b/src/main/scala/rocketchip/Configs.scala @@ -55,15 +55,15 @@ class DefaultL2FPGAConfig extends Config( class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config) class WithNMemoryChannels(n: Int) extends Config( - (pname,site,here) => pname match { - case BankedL2Config => site(BankedL2Config).copy(nMemoryChannels = n) + (pname,site,here,up) => pname match { + case BankedL2Config => up(BankedL2Config).copy(nMemoryChannels = n) case _ => throw new CDEMatchError } ) class WithExtMemSize(n: Long) extends Config( - (pname,site,here) => pname match { - case ExtMem => site(ExtMem).copy(size = n) + (pname,site,here,up) => pname match { + case ExtMem => up(ExtMem).copy(size = n) case _ => throw new CDEMatchError } ) @@ -93,8 +93,8 @@ class DualChannelDualBankL2Config extends Config( class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig) class WithEdgeDataBits(dataBits: Int) extends Config( - (pname, site, here) => pname match { - case ExtMem => site(ExtMem).copy(beatBytes = dataBits/8) + (pname, site, here, up) => pname match { + case ExtMem => up(ExtMem).copy(beatBytes = dataBits/8) case _ => throw new CDEMatchError })