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axi4 ToTL: fix decode error arbitration (#417)

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When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
This commit is contained in:
Wesley W. Terpstra
2016-10-24 22:15:19 -07:00
committed by GitHub
parent 4c815f7958
commit a5ac106bb8
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/axi4/ToTL.scala
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@@ -130,8 +130,8 @@ class AXI4ToTL extends LazyModule
// Prioritize err over ok (b/c err_r.valid comes from a register)
mux_r.valid := (!mux_lock_err && ok_r.valid) || (!mux_lock_ok && err_r.valid)
mux_r.bits := Mux(!mux_lock_ok && err_r.valid, err_r.bits, ok_r.bits)
ok_r.ready := !mux_lock_err && mux_r.ready && !err_r.valid
err_r.ready := !mux_lock_ok && mux_r.ready
ok_r.ready := mux_r.ready && (mux_lock_ok || !err_r.valid)
err_r.ready := mux_r.ready && !mux_lock_ok
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(mux_r, 1, flow=true)