From a59a3f15e4c7373f1ec6269422260826455cb152 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 14 Apr 2017 18:23:44 -0700 Subject: [PATCH] Disable LR/SC tests for scratchpad configs --- src/main/scala/rocketchip/Generator.scala | 4 +++- src/main/scala/rocketchip/RocketTestSuite.scala | 7 ++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala index 9ae0b74b..127c7fed 100644 --- a/src/main/scala/rocketchip/Generator.scala +++ b/src/main/scala/rocketchip/Generator.scala @@ -50,7 +50,8 @@ object Generator extends util.GeneratorApp { import DefaultTestSuites._ val xlen = params(XLen) // TODO: for now only generate tests for the first core in the first coreplex - val coreParams = params(RocketTilesKey).head.core + val tileParams = params(RocketTilesKey).head + val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => @@ -68,6 +69,7 @@ object Generator extends util.GeneratorApp { } if (coreParams.useAtomics) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useAtomics && tileParams.dcache.flatMap(_.scratch).isEmpty) TestGeneration.addSuites(env.map(if (xlen == 64) rv64lrsc else rv32lrsc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) diff --git a/src/main/scala/rocketchip/RocketTestSuite.scala b/src/main/scala/rocketchip/RocketTestSuite.scala index 0e94e47b..de737136 100644 --- a/src/main/scala/rocketchip/RocketTestSuite.scala +++ b/src/main/scala/rocketchip/RocketTestSuite.scala @@ -120,9 +120,12 @@ object DefaultTestSuites { val rv32umNames = LinkedHashSet("mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu") val rv32um = new AssemblyTestSuite("rv32um", rv32umNames)(_) - val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w") + val rv32uaNames = LinkedHashSet("amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w") val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_) + val rv32lrscNames = LinkedHashSet("lrsc") + val rv32lrsc = new AssemblyTestSuite("rv32ua", rv32lrscNames)(_) + val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi", "dirty") val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_) @@ -142,6 +145,8 @@ object DefaultTestSuites { val rv64uaNames = rv32uaNames.map(_.replaceAll("_w","_d")) val rv64ua = new AssemblyTestSuite("rv64ua", rv32uaNames ++ rv64uaNames)(_) + val rv64lrsc = new AssemblyTestSuite("rv64ua", rv32lrscNames)(_) + val rv64ucNames = rv32ucNames val rv64uc = new AssemblyTestSuite("rv64uc", rv64ucNames)(_)