riscv/rocket-chip
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add missing Wire wrap in BasicCrossbar

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Howard Mao 2015-08-05 17:05:31 -07:00
parent eb6583d607
commit a551a12d70
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/network.scala
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@ -27,7 +27,7 @@ abstract class PhysicalNetwork extends Module
class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork { class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork {
val io = new BasicCrossbarIO(n, dType) val io = new BasicCrossbarIO(n, dType)
val rdyVecs = List.fill(n){Vec.fill(n)(Bool())} val rdyVecs = List.fill(n){Vec.fill(n)(Wire(Bool()))}
io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => { io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock)) val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock))