diff --git a/chisel b/chisel
index e9a21c3d..a39c41ac 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit e9a21c3d67bde8ae7603774a58cae63db6382ca7
+Subproject commit a39c41ac3352fec1ec35b3e97c643f7e2f3843be
diff --git a/src/main/scala/Backends.scala b/src/main/scala/Backends.scala
index a712a811..d7db7042 100644
--- a/src/main/scala/Backends.scala
+++ b/src/main/scala/Backends.scala
@@ -62,9 +62,8 @@ class RocketChipBackend extends VerilogBackend
     initMap += (c -> init)
   }
 
-  transforms += ((c: Module) => addTopLevelPin(c))
-  transforms += ((c: Module) => addMemPin(c))
-  transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
+  transforms += addTopLevelPin
+  transforms += addMemPin
 }
 
 class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform