riscv/rocket-chip
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new build system with updated chisel, hwacha

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This commit is contained in:
Yunsup Lee 2012-02-14 19:43:59 -08:00
parent 0ec7767c13
commit a51c7cc927
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/dpath_alu.scala
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@ -37,7 +37,7 @@ class rocketDpathALU extends Component
val shin_hi = Mux(io.dw === DW_64, io.in1(63,32), shin_hi_32)
val shin_r = Cat(shin_hi, io.in1(31,0))
val shin = Mux(shright, shin_r, Reverse(shin_r))
val shout_r = (Cat(sra & shin_r(63), shin).toFix >>> shamt)(63,0)
val shout_r = (Cat(sra & shin_r(63), shin).toFix >> shamt)(63,0)
val logic =
Mux(io.fn === FN_AND, io.in1 & io.in2,