Clean up multiplier/divider stuff
This commit is contained in:
Andrew Waterman
parent
4d236979bd
commit
a50a1f7d50
@ -1,199 +0,0 @@
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package rocket
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import Chisel._
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import ALU._
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import Util._
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class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
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val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 7)
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val state = Reg(init=s_ready)
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val req = Reg(io.req.bits.clone)
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val count = Reg(UInt(width = log2Up(w+1)))
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val divby0 = Reg(Bool())
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val neg_out = Reg(Bool())
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val divisor = Reg(Bits(width = w+1)) // div only needs w bits
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val remainder = Reg(Bits(width = 2*mulw+2)) // div only needs 2*w+1 bits
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def sext(x: Bits, cmds: Vec[Bits]) = {
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val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM, FN_MULH, FN_MULHSU))
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM, FN_MULH))
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val subtractor = remainder(2*w,w) - divisor(w,0)
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val negated_remainder = -remainder(w-1,0)
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when (state === s_neg_inputs) {
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val isMul = AVec(FN_MUL, FN_MULH, FN_MULHU, FN_MULHSU).contains(req.fn)
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state := Mux(isMul, s_mul_busy, s_div_busy)
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when (remainder(w-1) || isMul) {
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remainder := negated_remainder
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}
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when (divisor(w-1) || isMul) {
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divisor := subtractor
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}
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}
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when (state === s_neg_output) {
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remainder := negated_remainder
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state := s_done
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_mul_busy) {
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val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
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val mplier = mulReg(mulw-1,0)
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val accum = mulReg(2*mulw,mulw).toSInt
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val mpcand = divisor.toSInt
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val prod = mplier(mulUnroll-1,0) * mpcand + accum
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val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
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remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
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count := count + 1
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when (count === mulw/mulUnroll-1) {
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state := s_done
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when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) {
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state := s_move_rem
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}
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}
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}
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when (state === s_div_busy) {
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when (count === UInt(w)) {
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state := Mux(neg_out && !divby0, s_neg_output, s_done)
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when (AVec(FN_REM, FN_REMU) contains req.fn) {
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state := s_move_rem
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}
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}
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count := count + UInt(1)
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val msb = subtractor(w)
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divby0 := divby0 && !msb
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remainder := Cat(Mux(msb, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !msb)
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val divisorMSB = Log2(divisor(w-1,0), w)
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val dividendMSB = Log2(remainder(w-1,0), w)
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val eOutPos = UInt(w-1) + divisorMSB - dividendMSB
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val eOutZero = divisorMSB > dividendMSB
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val eOut = count === UInt(0) && (eOutPos > 0 || eOutZero) && (divisorMSB != UInt(0) || divisor(0))
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when (Bool(earlyOut) && eOut) {
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val shift = Mux(eOutZero, UInt(w-1), eOutPos)
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remainder := remainder(w-1,0) << shift
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count := shift
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}
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}
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when (io.resp.fire() || io.kill) {
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state := s_ready
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}
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when (io.req.fire()) {
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val isMul = AVec(FN_MUL, FN_MULH, FN_MULHU, FN_MULHSU).contains(io.req.bits.fn)
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val isRem = AVec(FN_REM, FN_REMU).contains(io.req.bits.fn)
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val mulState = Mux(lhs_sign, s_neg_inputs, s_mul_busy)
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val divState = Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div_busy)
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state := Mux(isMul, mulState, divState)
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count := UInt(0)
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neg_out := !isMul && Mux(isRem, lhs_sign, lhs_sign != rhs_sign)
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divby0 := true
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divisor := Cat(rhs_sign, rhs_in)
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remainder := lhs_in
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req := io.req.bits
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}
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io.resp.bits := req
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io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.valid := state === s_done
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io.req.ready := state === s_ready
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}
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class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(w+1)))
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val divby0 = Reg(Bool())
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val neg_out = Reg(Bool())
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val r_req = Reg(io.req.bits)
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val divisor = Reg(Bits())
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val remainder = Reg(Bits(width = 2*w+1))
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val subtractor = remainder(2*w,w) - divisor
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def sext(x: Bits, cmds: Vec[Bits]) = {
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val sign = Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) && cmds.contains(io.req.bits.fn)
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, AVec(FN_DIV, FN_REM))
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, AVec(FN_DIV, FN_REM))
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val r_isRem = isMulFN(r_req.fn, FN_REM) || isMulFN(r_req.fn, FN_REMU)
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when (state === s_neg_inputs) {
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state := s_busy
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when (remainder(w-1)) {
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remainder := -remainder(w-1,0)
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}
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when (divisor(w-1)) {
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divisor := subtractor(w-1,0)
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}
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}
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when (state === s_neg_output) {
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remainder := -remainder(w-1,0)
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state := s_done
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_busy) {
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when (count === UInt(w)) {
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state := Mux(r_isRem, s_move_rem, Mux(neg_out && !divby0, s_neg_output, s_done))
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}
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count := count + UInt(1)
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val msb = subtractor(w)
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divby0 := divby0 && !msb
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remainder := Cat(Mux(msb, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !msb)
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val divisorMSB = Log2(divisor, w)
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val dividendMSB = Log2(remainder(w-1,0), w)
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val eOutPos = UInt(w-1, log2Up(2*w)) + divisorMSB - dividendMSB
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val eOut = count === UInt(0) && eOutPos > 0 && (divisorMSB != UInt(0) || divisor(0))
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when (Bool(earlyOut) && eOut) {
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val shift = eOutPos(log2Up(w)-1,0)
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remainder := remainder(w-1,0) << shift
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count := shift
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when (eOutPos(log2Up(w))) {
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remainder := remainder(w-1,0) << w-1
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count := w-1
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}
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}
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}
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when (io.resp.fire() || io.kill) {
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state := s_ready
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}
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when (io.req.fire()) {
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state := Mux(lhs_sign || rhs_sign, s_neg_inputs, s_busy)
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count := UInt(0)
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neg_out := Mux(AVec(FN_REM, FN_REMU).contains(io.req.bits.fn), lhs_sign, lhs_sign != rhs_sign)
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divby0 := true
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divisor := rhs_in
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remainder := lhs_in
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r_req := io.req.bits
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}
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io.resp.bits := r_req
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io.resp.bits.data := Mux(r_req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.valid := state === s_done
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io.req.ready := state === s_ready
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}
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@ -2,6 +2,7 @@ package rocket
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import Chisel._
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import ALU._
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import Util._
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class MultiplierReq(implicit conf: RocketConfiguration) extends Bundle {
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val fn = Bits(width = SZ_ALU_FN)
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@ -26,68 +27,113 @@ class MultiplierIO(implicit conf: RocketConfiguration) extends Bundle {
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val resp = Decoupled(new MultiplierResp)
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}
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class Multiplier(unroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
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class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: RocketConfiguration) extends Module {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
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val w0 = io.req.bits.in1.getWidth
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val w = (w0+1+unroll-1)/unroll*unroll
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val cycles = w/unroll
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val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_ready)
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val r_val = Reg(init=Bool(false))
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val r_prod = Reg(Bits(width = w*2))
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val r_lsb = Reg(Bits())
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val r_cnt = Reg(UInt(width = log2Up(cycles+1)))
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val r_req = Reg(new MultiplierReq)
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val r_lhs = Reg(Bits(width = w0+1))
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val req = Reg(io.req.bits)
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val count = Reg(UInt(width = log2Up(w+1)))
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val neg_out = Reg(Bool())
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val isMul = Reg(Bool())
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val isHi = Reg(Bool())
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val divisor = Reg(Bits(width = w+1)) // div only needs w bits
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val remainder = Reg(Bits(width = 2*mulw+2)) // div only needs 2*w+1 bits
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val dw = io.req.bits.dw
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val fn = io.req.bits.fn
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val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
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DecodeLogic(io.req.bits.fn, List(X, X, X, X), List(
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FN_DIV -> List(N, N, Y, Y),
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FN_REM -> List(N, Y, Y, Y),
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FN_DIVU -> List(N, N, N, N),
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FN_REMU -> List(N, Y, N, N),
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FN_MUL -> List(Y, N, X, X),
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FN_MULH -> List(Y, Y, Y, Y),
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FN_MULHU -> List(Y, Y, N, N),
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FN_MULHSU -> List(Y, Y, Y, N)))
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val lhs_msb = Mux(dw === DW_64, io.req.bits.in1(w0-1), io.req.bits.in1(w0/2-1)).toBool
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val lhs_sign = (isMulFN(fn, FN_MULH) || isMulFN(fn, FN_MULHSU)) && lhs_msb
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val lhs_hi = Mux(dw === DW_64, io.req.bits.in1(w0-1,w0/2), Fill(w0/2, lhs_sign))
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val lhs_in = Cat(lhs_sign, lhs_hi, io.req.bits.in1(w0/2-1,0))
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def sext(x: Bits, signed: Bool) = {
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val sign = signed && Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1))
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, lhsSigned)
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, rhsSigned)
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val rhs_msb = Mux(dw === DW_64, io.req.bits.in2(w0-1), io.req.bits.in2(w0/2-1)).toBool
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val rhs_sign = isMulFN(fn, FN_MULH) && rhs_msb
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val rhs_hi = Mux(dw === DW_64, io.req.bits.in2(w0-1,w0/2), Fill(w0/2, rhs_sign))
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val rhs_in = Cat(Fill(w-w0, rhs_sign), rhs_hi, io.req.bits.in2(w0/2-1,0))
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val subtractor = remainder(2*w,w) - divisor(w,0)
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val less = subtractor(w)
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val negated_remainder = -remainder(w-1,0)
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when (state === s_neg_inputs) {
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when (remainder(w-1) || isMul) {
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remainder := negated_remainder
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}
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when (divisor(w-1) || isMul) {
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divisor := subtractor
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}
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state := s_busy
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}
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when (state === s_neg_output) {
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remainder := negated_remainder
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state := s_done
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_busy && isMul) {
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val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
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val mplier = mulReg(mulw-1,0)
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val accum = mulReg(2*mulw,mulw).toSInt
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val mpcand = divisor.toSInt
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val prod = mplier(mulUnroll-1,0) * mpcand + accum
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val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
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remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
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count := count + 1
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when (count === mulw/mulUnroll-1) {
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state := Mux(isHi, s_move_rem, s_done)
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}
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}
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when (state === s_busy && !isMul) {
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when (count === w) {
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state := Mux(isHi, s_move_rem, Mux(neg_out, s_neg_output, s_done))
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}
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count := count + 1
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remainder := Cat(Mux(less, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !less)
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val divisorMSB = Log2(divisor(w-1,0), w)
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val dividendMSB = Log2(remainder(w-1,0), w)
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val eOutPos = UInt(w-1) + divisorMSB - dividendMSB
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val eOutZero = divisorMSB > dividendMSB
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val eOut = count === 0 && less /* not divby0 */ && (eOutPos > 0 || eOutZero)
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when (Bool(earlyOut) && eOut) {
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val shift = Mux(eOutZero, UInt(w-1), eOutPos(log2Up(w)-1,0))
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remainder := remainder(w-1,0) << shift
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count := shift
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}
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when (count === 0 && !less /* divby0 */) { neg_out := false }
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}
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when (io.resp.fire() || io.kill) {
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state := s_ready
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}
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when (io.req.fire()) {
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r_val := Bool(true)
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r_cnt := UInt(0, log2Up(cycles+1))
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r_req := io.req.bits
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r_lhs := lhs_in
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r_prod:= rhs_in
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r_lsb := Bool(false)
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}
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.elsewhen (io.resp.fire() || io.kill) {
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r_val := Bool(false)
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state := Mux(lhs_sign || rhs_sign && !cmdMul, s_neg_inputs, s_busy)
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isMul := cmdMul
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isHi := cmdHi
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count := 0
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neg_out := !cmdMul && Mux(cmdHi, lhs_sign, lhs_sign != rhs_sign)
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divisor := Cat(rhs_sign, rhs_in)
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remainder := lhs_in
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req := io.req.bits
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}
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val eOutDist = (UInt(cycles)-r_cnt)*UInt(unroll)
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val outShift = Mux(isMulFN(r_req.fn, FN_MUL), UInt(0), Mux(r_req.dw === DW_64, UInt(64), UInt(32)))
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val shiftDist = Mux(r_cnt === UInt(cycles), outShift, eOutDist)
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val eOutMask = (UInt(1) << eOutDist) - UInt(1)
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val eOut = r_cnt != UInt(0) && Bool(earlyOut) && !((r_prod(w-1,0) ^ r_lsb.toSInt) & eOutMask).orR
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val shift = r_prod.toSInt >> shiftDist
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val sum = r_prod(2*w-1,w).toSInt + r_prod(unroll-1,0).toSInt * r_lhs.toSInt + Mux(r_lsb.toBool, r_lhs.toSInt, SInt(0))
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when (r_val && (r_cnt != UInt(cycles))) {
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r_lsb := r_prod(unroll-1)
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r_prod := Cat(sum, r_prod(w-1,unroll)).toSInt
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r_cnt := r_cnt + UInt(1)
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when (eOut) {
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r_prod := shift
|
||||
r_cnt := UInt(cycles)
|
||||
}
|
||||
}
|
||||
|
||||
val out32 = Cat(Fill(w0/2, shift(w0/2-1)), shift(w0/2-1,0))
|
||||
val out64 = shift(w0-1,0)
|
||||
|
||||
io.req.ready := !r_val
|
||||
io.resp.bits := r_req
|
||||
io.resp.bits.data := Mux(r_req.dw === DW_64, out64, out32)
|
||||
io.resp.valid := r_val && (r_cnt === UInt(cycles))
|
||||
io.resp.bits := req
|
||||
io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
|
||||
io.resp.valid := state === s_done
|
||||
io.req.ready := state === s_ready
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user