riscv/rocket-chip
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fix icache prefetch global_xact_id bug

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This commit is contained in:
Henry Cook 2012-03-11 00:48:29 -08:00
parent 1aa4b0e93d
commit a4d0025187
1 changed files with 4 additions and 3 deletions
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5
rocket/src/main/scala/icache_prefetch.scala
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@ -60,11 +60,12 @@ class rocketIPrefetcher extends Component() {
io.icache.xact_rep.valid := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid) io.icache.xact_rep.valid := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid)
io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data) io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data)
io.icache.xact_rep.bits.require_ack := !forward && io.mem.xact_rep.bits.require_ack io.icache.xact_rep.bits.require_ack := !forward && io.mem.xact_rep.bits.require_ack
io.icache.xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false)) pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
pdq.io.enq.bits := io.mem.xact_rep.bits.data pdq.io.enq.bits := io.mem.xact_rep.bits.data
pdq.io.enq.valid := ip_mem_resp_val.toBool; pdq.io.enq.valid := ip_mem_resp_val
pdq.io.deq.ready := forward; pdq.io.deq.ready := forward
switch (state) { switch (state) {
is (s_invalid) { is (s_invalid) {