Broadcast hub control logic bugfixes and code cleanup
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802f857cb6
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a49625c114
@ -26,18 +26,13 @@ class ioMem() extends Bundle
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val resp = (new ioPipe) { new MemResp() }.flip
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val resp = (new ioPipe) { new MemResp() }.flip
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}
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}
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class HubMemReq extends Bundle {
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val lock = Bool()
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}
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class TrackerProbeData extends Bundle {
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class TrackerProbeData extends Bundle {
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val tile_id = Bits(width = TILE_ID_BITS)
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val tile_id = Bits(width = TILE_ID_BITS)
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}
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}
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class TrackerAllocReq extends Bundle {
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class TrackerAllocReq extends Bundle {
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val xact_init = new TransactionInit()
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val xact_init = new TransactionInit()
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val init_tile_id = Bits(width = TILE_ID_BITS)
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val tile_id = Bits(width = TILE_ID_BITS)
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val data_valid = Bool()
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}
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}
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@ -98,8 +93,7 @@ object cpuCmdToRW {
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}
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}
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}
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}
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trait CoherencePolicy {
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trait CoherencePolicy { }
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}
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trait ThreeStateIncoherence extends CoherencePolicy {
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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@ -242,36 +236,18 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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(t_type === X_INIT_WRITE_UNCACHED)
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioDecoupled[MemData], trigger: Bool, pop_data: Bool, cmd_sent: Bool) {
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val state = Reg(resetVal = s_idle)
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req_cmd.valid := !cmd_sent
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val addr_ = Reg{ UFix() }
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = Bits(0, width = NTILES))
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val p_rep_tile_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioDecoupled[MemData], trigger: Bool, pop: Bool) {
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req_cmd.valid := mem_cmd_sent
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req_cmd.bits.rw := Bool(true)
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req_cmd.bits.rw := Bool(true)
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//TODO: why does req_data <> data segfault?
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req_data.valid := data.valid
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req_data.bits.data := data.bits.data
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data.ready := req_data.ready
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data.ready := req_data.ready
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req_data <> data
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lock := Bool(true)
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lock := Bool(true)
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when(req_cmd.ready && req_cmd.valid) {
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when(req_cmd.ready && req_cmd.valid) {
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mem_cmd_sent := Bool(false)
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cmd_sent := Bool(true)
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}
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}
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when(req_data.ready && req_data.valid) {
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when(req_data.ready && req_data.valid) {
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pop := Bool(true)
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pop_data := Bool(true)
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mem_cnt := mem_cnt_next
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mem_cnt := mem_cnt_next
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}
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}
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when(mem_cnt === ~UFix(0)) {
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when(mem_cnt === ~UFix(0)) {
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trigger := Bool(false)
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trigger := Bool(false)
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@ -286,6 +262,25 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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}
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}
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}
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val addr_ = Reg{ UFix() }
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = Bits(0, width = NTILES))
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val p_rep_tile_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2up(REFILL_CYCLES))
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io.busy := state != s_idle
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io.busy := state != s_idle
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io.addr := addr_
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io.addr := addr_
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io.init_tile_id := init_tile_id_
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io.init_tile_id := init_tile_id_
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@ -318,16 +313,16 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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when( io.alloc_req.valid && io.can_alloc ) {
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when( io.alloc_req.valid && io.can_alloc ) {
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addr_ := io.alloc_req.bits.xact_init.address
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addr_ := io.alloc_req.bits.xact_init.address
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t_type_ := io.alloc_req.bits.xact_init.t_type
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t_type_ := io.alloc_req.bits.xact_init.t_type
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init_tile_id_ := io.alloc_req.bits.init_tile_id
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init_tile_id_ := io.alloc_req.bits.tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
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x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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p_rep_count := UFix(NTILES-1)
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p_rep_count := UFix(NTILES-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.init_tile_id )
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id )
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state := Mux(p_req_flags.orR, s_probe, s_mem)
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mem_cnt := UFix(0)
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mem_cnt := UFix(0)
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mem_cmd_sent := Bool(false)
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mem_cmd_sent := Bool(false)
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io.pop_x_init := Bool(true)
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io.pop_x_init := Bool(true)
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state := Mux(p_req_flags.orR, s_probe, s_mem)
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}
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}
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}
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}
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is(s_probe) {
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is(s_probe) {
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@ -342,9 +337,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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io.pop_p_rep := io.p_rep_cnt_dec
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io.pop_p_rep := io.p_rep_cnt_dec
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p_rep_count := p_rep_count_next
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p_rep_count := p_rep_count_next
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when(p_rep_count_next === UFix(0)) {
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when(p_rep_count === UFix(0)) {
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mem_cnt := UFix(0)
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io.pop_p_rep := Bool(true)
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mem_cmd_sent := Bool(false)
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state := s_mem
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state := s_mem
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}
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}
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}
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}
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@ -355,9 +349,9 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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}
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}
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is(s_mem) {
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is(s_mem) {
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when (p_rep_data_needs_write) {
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when (p_rep_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.p_rep_data, p_rep_data_needs_write, io.pop_p_rep_data)
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.p_rep_data, p_rep_data_needs_write, io.pop_p_rep_data, p_w_mem_cmd_sent)
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} . elsewhen(x_init_data_needs_write) {
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} . elsewhen(x_init_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.x_init_data, x_init_data_needs_write, io.pop_x_init_data)
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.x_init_data, x_init_data_needs_write, io.pop_x_init_data, x_w_mem_cmd_sent)
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} . elsewhen (x_needs_read) {
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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} . otherwise {
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@ -565,10 +559,9 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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val x_init_data = io.tiles(j).xact_init_data
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val x_init_data = io.tiles(j).xact_init_data
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init_arb.io.in(j).valid := x_init.valid
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init_arb.io.in(j).valid := x_init.valid
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init_arb.io.in(j).bits.xact_init := x_init.bits
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init_arb.io.in(j).bits.xact_init := x_init.bits
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init_arb.io.in(j).bits.init_tile_id := UFix(j)
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init_arb.io.in(j).bits.tile_id := UFix(j)
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init_arb.io.in(j).bits.data_valid := x_init_data.valid
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x_init.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.tile_id === UFix(j)))(_||_)
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x_init.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.init_tile_id === UFix(j)))(_||_)
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x_init_data.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.tile_id === UFix(j)))(_||_)
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x_init_data.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.init_tile_id === UFix(j)))(_||_)
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}
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}
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alloc_arb.io.out.ready := init_arb.io.out.valid && !busy_arr.toBits.andR &&
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alloc_arb.io.out.ready := init_arb.io.out.valid && !busy_arr.toBits.andR &&
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