riscv/rocket-chip
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tilelink2: change adapters to use TLAdapter(params, defaults)(node)

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This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
This commit is contained in:
Wesley W. Terpstra
2016-09-22 17:45:42 -07:00
parent a1d5102da9
commit a421469754
7 changed files with 17 additions and 17 deletions
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2
src/main/scala/rocketchip/BaseTop.scala
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@ -49,7 +49,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
}
abstract class BaseTopBundle(val p: Parameters) extends Bundle {

6
src/main/scala/rocketchip/Periphery.scala
View File

@ -288,7 +288,7 @@ trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryPara
val clintConfig = CoreplexLocalInterrupterConfig(beatBytes)
val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
// The periphery bus is 32-bit, so we may need to adapt its width to XLen
clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
clint.node := TLFragmenter(beatBytes, 256)(TLWidthWidget(4)(peripheryBus.node))
}
trait PeripheryCoreplexLocalInterrupterBundle {
@ -314,7 +314,7 @@ trait PeripheryBootROM extends LazyModule {
val address = 0x1000
val size = 0x1000
val rom = LazyModule(new TLROM(address, size, GenerateBootROM(p, address)) { override def name = "bootrom" })
rom.node := TLFragmenter(peripheryBus.node, 4, 256)
rom.node := TLFragmenter(4, 256)(peripheryBus.node)
}
trait PeripheryBootROMBundle {
@ -337,7 +337,7 @@ trait PeripheryTestRAM extends LazyModule {
val ramSize = 0x1000
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)) { override def name = "testram" })
sram.node := TLFragmenter(peripheryBus.node, 4, 256)
sram.node := TLFragmenter(4, 256)(peripheryBus.node)
}
trait PeripheryTestRAMBundle {