Final parameter refactor.
This commit is contained in:
Henry Cook
parent
2741bbf2b9
commit
a41d55b643
2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 4728ab65aca8a47b3889d7fe5006553cda9a0a4c
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Subproject commit 00d24693d4b656508fc50b48f411057d06c38f4d
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2
rocket
2
rocket
@ -1 +1 @@
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Subproject commit 50c5310b56d589a0e626d4c68cb8cd73a698727e
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Subproject commit 54fe89fe3bdc9e9cd2caf7adab68bb6bb81b2b9c
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145
src/main/scala/PublicConfigs.scala
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145
src/main/scala/PublicConfigs.scala
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@ -0,0 +1,145 @@
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package referencechip
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import Chisel._
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import uncore._
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import rocket._
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import rocket.Util._
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultFPGAConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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class DefaultConfig extends ChiselConfig {
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val top:World.TopDefs = {
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(pname,site,here) => pname match {
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//Params used by all caches
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case ECCCode => None
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case WordBits => site(XprLen)
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case Replacer => () => new RandomReplacement(site(NWays))
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case BlockOffBits => site(CacheName) match {
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case "L1I" | "L1D" => log2Up(site(TLDataBits)/8)
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case "L2" => 0
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}
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case NSets => site(CacheName) match {
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case "L1I" => 128
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case "L1D" => 128
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case "L2" => 512
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}
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case NWays => site(CacheName) match {
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case "L1I" => 2
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case "L1D" => 4
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case "L2" => 8
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}
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case RowBits => site(CacheName) match {
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case "L1I" => 4*site(CoreInstBits)
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case "L1D" => 2*site(CoreDataBits)
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case "L2" => site(TLDataBits)
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}
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//L1InstCache
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case NITLBEntries => 8
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case NBTBEntries => 62
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case NRAS => 2
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//L1DataCache
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case NDTLBEntries => 8
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => site[Int]("NMSHRS")
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case LRSCCycles => 32
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//L2CacheParams
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case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
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case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
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case NClients => site(NTiles) + 1
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//Tile Constants
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
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//Rocket Core Constants
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XprLen => 64
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case NMultXpr => 32
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case BuildFPU => Some(() => new FPU)
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XprLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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//HTIF Parameters
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFDataBeats => 4
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//Uncore Paramters
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case LNMasters => site(NBanks)
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case LNClients => site(NTiles)+1
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case LNEndpoints => site(LNMasters) + site(LNClients)
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case TLCoherence => site(Coherence)
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case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
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case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
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case TLDataBits => site(CacheBlockBytes)*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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case NTiles => here[Int]("NTILES")
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case NBanks => here[Int]("NBANKS")
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case BankIdLSB => 5
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case BuildDRAMSideLLC => () => {
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val refill = site(TLDataBits)/site(MIFDataBits)
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if(site[Boolean]("USE_DRAMSIDE_LLC")) {
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val tag = Mem(Bits(width = 152), 512, seqRead = true)
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val data = Mem(Bits(width = 64), 4096, seqRead = true)
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Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
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} else { Module(new DRAMSideLLCNull(16, refill)) }
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}
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case BuildCoherentMaster => (id: Int) => {
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if(!site[Boolean]("USE_DRAMSIDE_LLC")) {
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Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
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} else {
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Module(new L2HellaCache(id), { case CacheName => "L2" })
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}
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}
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case Coherence => {
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val dir = new FullRepresentation(site(NClients))
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val enSharing = site[Boolean]("ENABLE_SHARING")
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val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
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if(enSharing) {
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if(enCleanEx) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(enCleanEx) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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}
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//DesignSpaceConstants //TODO KNOBS
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case "NTILES" => 1
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case "NBANKS" => 1
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case "HTIF_WIDTH" => 16
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case "ENABLE_SHARING" => true
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case "ENABLE_CLEAN_EXCLUSIVE" => true
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case "USE_DRAMSIDE_LLC" => true
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case "NL2_REL_XACTS" => 1
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case "NL2_ACQ_XACTS" => 7
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case "NMSHRS" => 2
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}
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}
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}
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@ -5,160 +5,13 @@ import uncore._
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import rocket._
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import rocket.Util._
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultFPGAConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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class DefaultConfig extends ChiselConfig {
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val top:World.TopDefs = {
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(pname,site,here) => pname match {
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//DesignSpaceConstants
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case "NTILES" => 1
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case "NBANKS" => 1
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case "HTIF_WIDTH" => 16
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case "ENABLE_SHARING" => true
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case "ENABLE_CLEAN_EXCLUSIVE" => true
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case "USE_DRAMSIDE_LLC" => true
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case "NL2_REL_XACTS" => 1
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case "NL2_ACQ_XACTS" => 7
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case "NMSHRS" => 2
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//Coherence
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case Coherence => {
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val dir = new FullRepresentation(site[Int]("NTILES")+1)
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if(site[Boolean]("ENABLE_SHARING")) {
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if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir)
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else new MSICoherence(dir)
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} else {
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if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir)
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else new MICoherence(dir)
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}
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}
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//Rocket Constants
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// Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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// Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc
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case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case BuildRoCC => None
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case DcacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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case XprLen => 64
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case NXpr => 32
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case NXprBits => log2Up(here(NXpr))
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case BuildFPU => Some(() => new FPU)
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case FPUParams => Alter({
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case SFMALatency => 2
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case DFMALatency => 3
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})
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case RocketDCacheParams => Alter({
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//L1 Specific
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => site[Int]("NMSHRS")
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case NTLBEntries => 8
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case CoreReqTagBits => site(DcacheReqTagBits)
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case CoreDataBits => site(XprLen)
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case ECCCode => new IdentityCode
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case LRSCCycles => 32
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//From uncore/cache.scala
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case NSets => 128
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case NWays => 4
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case BlockOffBits => log2Up(site(TLDataBits)/8)
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case RowBits => 2*site(XprLen)
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case WordBits => site(XprLen) //here(CoreDataBits) TODO
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case Replacer => () => new RandomReplacement(4)//site(NWays)) TODO
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})
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case RocketFrontendParams => Alter({
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case InstBytes => 4
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case NTLBEntries => 8
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case ECCCode => new IdentityCode
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//From rocket/btb.scala
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case BTBEntries => 62
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case NRAS => 2
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//From uncore/cache.scala
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case NSets => 128
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case NWays => 2
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case BlockOffBits => log2Up(site(TLDataBits)/8)
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case RowBits => 16*8
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case WordBits => site(XprLen) //TODO merge with instbytes?
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case Replacer => () => new RandomReplacement(2)//site(NWays)) TODO
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})
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//MemoryConstants
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case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6
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case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES"))
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => here(PAddrBits) - here(PgIdxBits)
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case VPNBits => here(VAddrBits) - here(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => here(PAddrBits) - here[Int]("OFFSET_BITS")
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case MIFDataBeats => 4
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//Uncore Constants
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case TileLinkL1Params => Alter({
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case LNMasters => site[Int]("NBANKS")
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case LNClients => site[Int]("NTILES")+1
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case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients)
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case TLCoherence => site(Coherence)
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case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS")
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case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS"))
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case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1)
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case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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})
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case L2HellaCacheParams => Alter({
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case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
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case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
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case NClients => site[Int]("NTILES") + 1
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case NSets => 512
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case NWays => 8
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case BlockOffBits => 0
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case RowBits => site(TLDataBits)
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case WordBits => site(XprLen)
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case Replacer => () => new RandomReplacement(8)//site(NWays))
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})
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case NTiles => here[Int]("NTILES")
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case NBanks => here[Int]("NBANKS")
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case BankIdLSB => 5
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case BuildDRAMSideLLC => () => {
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val refill = site(TLDataBits)/site(MIFDataBits)
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if(site[Boolean]("USE_DRAMSIDE_LLC")) {
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val tag = Mem(Bits(width = 152), 512, seqRead = true)
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val data = Mem(Bits(width = 64), 4096, seqRead = true)
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Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
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refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
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} else { Module(new DRAMSideLLCNull(16, refill)) }
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}
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case BuildCoherentMaster => (id: Int, p: Some[Parameters]) => {
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if(!site[Boolean]("USE_DRAMSIDE_LLC")) {
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Module(new L2CoherenceAgent(id))(p)
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} else {
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Module(new L2HellaCache(id))(p)
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}
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}
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//HTIF Constants
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => here[Int]("OFFSET_BITS")
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case HTIFNCores => here[Int]("NTILES")
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}
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}
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}
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case object NTiles extends Field[Int]
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case object NBanks extends Field[Int]
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case object BankIdLSB extends Field[Int]
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case object TileLinkL1Params extends Field[PF]
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case object L2HellaCacheParams extends Field[PF]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike]
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case object BuildCoherentMaster extends Field[(Int,Option[Parameters]) => CoherenceAgent]
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case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent]
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case object Coherence extends Field[CoherencePolicyWithUncached]
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class OuterMemorySystem extends Module
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@ -174,10 +27,9 @@ class OuterMemorySystem extends Module
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val refill_cycles = params(TLDataBits)/params(MIFDataBits)
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val llc = params(BuildDRAMSideLLC)()
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val l2p = Some(params.alter(params(L2HellaCacheParams)))
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)(_,l2p))
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster))
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val net = Module(new ReferenceChipCrossbarNetwork)(l2p)
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val net = Module(new ReferenceChipCrossbarNetwork)
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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@ -310,13 +162,12 @@ class Top extends Module {
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//val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
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//val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val nTiles = params[Int]("NTILES")
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val nTiles = params(NTiles)
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val io = new VLSITopIO
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val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?
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val resetSigs = Vec.fill(nTiles){Bool()}
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val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient?
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val uncore = Module(new Uncore, tl)
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val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
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val uncore = Module(new Uncore)
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for (i <- 0 until nTiles) {
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val hl = uncore.io.htif(i)
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@ -14,7 +14,7 @@ class FPGAOuterMemorySystem extends Module {
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val mem = new MemIO
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}
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val master = Module(new L2CoherenceAgent(0), params(L2HellaCacheParams))
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val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"})
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val net = Module(new ReferenceChipCrossbarNetwork)
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters.head <> master.io.inner
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@ -88,8 +88,6 @@ class FPGATop extends Module {
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val nTiles = params(NTiles)
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val io = new FPGATopIO
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params.alter(params(TileLinkL1Params))
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val resetSigs = Vec.fill(nTiles){Bool()}
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val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
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val uncore = Module(new FPGAUncore)
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 37fdf25582b9c0ef48dceecb76416c955f0bc81e
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Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5
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