Final parameter refactor.

chisel

@@ -1 +1 @@
-Subproject commit 4728ab65aca8a47b3889d7fe5006553cda9a0a4c
+Subproject commit 00d24693d4b656508fc50b48f411057d06c38f4d

rocket

@@ -1 +1 @@
-Subproject commit 50c5310b56d589a0e626d4c68cb8cd73a698727e
+Subproject commit 54fe89fe3bdc9e9cd2caf7adab68bb6bb81b2b9c

src/main/scala/PublicConfigs.scala

@@ -0,0 +1,145 @@
+package referencechip
+
+import Chisel._
+import uncore._
+import rocket._
+import rocket.Util._
+
+class DefaultVLSIConfig extends DefaultConfig
+class DefaultFPGAConfig extends DefaultConfig
+class DefaultCPPConfig extends DefaultConfig
+class DefaultConfig extends ChiselConfig {
+  val top:World.TopDefs = {
+    (pname,site,here) => pname match {
+      //Params used by all caches
+      case ECCCode => None
+      case WordBits => site(XprLen)
+      case Replacer => () => new RandomReplacement(site(NWays))
+      case BlockOffBits => site(CacheName) match {
+        case "L1I" | "L1D" => log2Up(site(TLDataBits)/8)
+        case "L2" => 0
+      }
+      case NSets => site(CacheName) match {
+        case "L1I" => 128
+        case "L1D" => 128
+        case "L2" => 512 
+      }
+      case NWays => site(CacheName) match {
+        case "L1I" => 2
+        case "L1D" => 4
+        case "L2" => 8
+      }
+      case RowBits => site(CacheName) match {
+        case "L1I" => 4*site(CoreInstBits)
+        case "L1D" => 2*site(CoreDataBits)
+        case "L2" => site(TLDataBits)
+      }
+      //L1InstCache
+      case NITLBEntries => 8
+      case NBTBEntries => 62
+      case NRAS => 2
+      //L1DataCache
+      case NDTLBEntries => 8
+      case StoreDataQueueDepth => 17
+      case ReplayQueueDepth => 16
+      case NMSHRs => site[Int]("NMSHRS")
+      case LRSCCycles => 32 
+      //L2CacheParams
+      case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
+      case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
+      case NClients => site(NTiles) + 1
+      //Tile Constants
+      case BuildRoCC => None
+      case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) 
+      case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
+      case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
+      //Rocket Core Constants
+      case RetireWidth => 1
+      case UseVM => true
+      case FastLoadWord => true
+      case FastLoadByte => false
+      case FastMulDiv => true
+      case XprLen => 64
+      case NMultXpr => 32
+      case BuildFPU => Some(() => new FPU)
+      case SFMALatency => 2
+      case DFMALatency => 3
+      case CoreInstBits => 32
+      case CoreDataBits => site(XprLen)
+      case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
+      //HTIF Parameters
+      case HTIFWidth => 16
+      case HTIFNSCR => 64
+      case HTIFOffsetBits => site(CacheBlockOffsetBits)
+      case HTIFNCores => site(NTiles)
+      //Memory Parameters
+      case PAddrBits => 32
+      case VAddrBits => 43
+      case PgIdxBits => 13
+      case ASIdBits => 7
+      case PermBits => 6
+      case PPNBits => site(PAddrBits) - site(PgIdxBits)
+      case VPNBits => site(VAddrBits) - site(PgIdxBits)
+      case MIFTagBits => 5
+      case MIFDataBits => 128
+      case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
+      case MIFDataBeats => 4
+      //Uncore Paramters
+      case LNMasters => site(NBanks)
+      case LNClients => site(NTiles)+1
+      case LNEndpoints => site(LNMasters) + site(LNClients)
+      case TLCoherence => site(Coherence)
+      case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
+      case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
+      case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
+      case TLDataBits => site(CacheBlockBytes)*8
+      case TLWriteMaskBits => 6
+      case TLWordAddrBits  => 3
+      case TLAtomicOpBits  => 4
+      case NTiles => here[Int]("NTILES")
+      case NBanks => here[Int]("NBANKS")
+      case BankIdLSB => 5
+      case CacheBlockBytes => 64
+      case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
+      case BuildDRAMSideLLC => () => {
+        val refill = site(TLDataBits)/site(MIFDataBits)
+        if(site[Boolean]("USE_DRAMSIDE_LLC")) {
+          val tag = Mem(Bits(width = 152), 512, seqRead = true)
+          val data = Mem(Bits(width = 64), 4096, seqRead = true)
+          Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, 
+            refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
+        } else { Module(new DRAMSideLLCNull(16, refill)) }
+      }
+      case BuildCoherentMaster => (id: Int) => {
+        if(!site[Boolean]("USE_DRAMSIDE_LLC")) { 
+          Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
+        } else {
+          Module(new L2HellaCache(id), { case CacheName => "L2" })
+        }
+      }
+      case Coherence => {
+        val dir = new FullRepresentation(site(NClients))
+        val enSharing = site[Boolean]("ENABLE_SHARING")
+        val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
+        if(enSharing) {
+          if(enCleanEx) new MESICoherence(dir)
+          else new MSICoherence(dir)
+        } else {
+          if(enCleanEx) new MEICoherence(dir)
+          else new MICoherence(dir)
+        }
+      }
+      //DesignSpaceConstants  //TODO KNOBS
+      case "NTILES" => 1
+      case "NBANKS" => 1
+      case "HTIF_WIDTH" => 16
+      case "ENABLE_SHARING" => true
+      case "ENABLE_CLEAN_EXCLUSIVE" => true
+      case "USE_DRAMSIDE_LLC" => true
+      case "NL2_REL_XACTS" => 1
+      case "NL2_ACQ_XACTS" => 7
+      case "NMSHRS" => 2
+    }
+  }
+}
+

src/main/scala/RocketChip.scala

@@ -5,160 +5,13 @@ import uncore._
 import rocket._
 import rocket.Util._
 
-class DefaultVLSIConfig extends DefaultConfig
-class DefaultFPGAConfig extends DefaultConfig
-class DefaultCPPConfig extends DefaultConfig
-class DefaultConfig extends ChiselConfig {
-  val top:World.TopDefs = {
-    (pname,site,here) => pname match {
-      //DesignSpaceConstants 
-      case "NTILES" => 1
-      case "NBANKS" => 1
-      case "HTIF_WIDTH" => 16
-      case "ENABLE_SHARING" => true
-      case "ENABLE_CLEAN_EXCLUSIVE" => true
-      case "USE_DRAMSIDE_LLC" => true
-      case "NL2_REL_XACTS" => 1
-      case "NL2_ACQ_XACTS" => 7
-      case "NMSHRS" => 2
-      //Coherence
-      case Coherence => {
-          val dir = new FullRepresentation(site[Int]("NTILES")+1)
-          if(site[Boolean]("ENABLE_SHARING")) {
-            if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir)
-            else new MSICoherence(dir)
-          } else {
-            if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir)
-            else new MICoherence(dir)
-          }
-        }
-      //Rocket Constants
-      // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC
-      case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) 
-      // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc
-      case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
-      case BuildRoCC => None
-      case RetireWidth => 1
-      case UseVM => true
-      case FastLoadWord => true
-      case FastLoadByte => false
-      case FastMulDiv => true
-      case DcacheReqTagBits => 7 + log2Up(here(NDCachePorts))
-      case XprLen => 64
-      case NXpr => 32
-      case NXprBits => log2Up(here(NXpr))
-      case BuildFPU => Some(() => new FPU)
-      case FPUParams => Alter({ 
-          case SFMALatency => 2
-          case DFMALatency => 3
-        })
-      case RocketDCacheParams => Alter({
-          //L1 Specific
-          case StoreDataQueueDepth => 17
-          case ReplayQueueDepth => 16
-          case NMSHRs => site[Int]("NMSHRS")
-          case NTLBEntries => 8
-          case CoreReqTagBits => site(DcacheReqTagBits)
-          case CoreDataBits => site(XprLen)
-          case ECCCode => new IdentityCode
-          case LRSCCycles => 32 
-          //From uncore/cache.scala
-          case NSets => 128
-          case NWays => 4
-          case BlockOffBits => log2Up(site(TLDataBits)/8)
-          case RowBits => 2*site(XprLen)
-          case WordBits => site(XprLen) //here(CoreDataBits) TODO
-          case Replacer => () => new RandomReplacement(4)//site(NWays)) TODO
-        })
-      case RocketFrontendParams => Alter({
-          case InstBytes => 4
-          case NTLBEntries => 8
-          case ECCCode => new IdentityCode
-          //From rocket/btb.scala
-          case BTBEntries => 62
-          case NRAS => 2
-          //From uncore/cache.scala
-          case NSets => 128
-          case NWays => 2
-          case BlockOffBits => log2Up(site(TLDataBits)/8)
-          case RowBits => 16*8
-          case WordBits => site(XprLen) //TODO merge with instbytes?
-          case Replacer => () => new RandomReplacement(2)//site(NWays)) TODO
-        })
-      //MemoryConstants
-      case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6
-      case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES"))
-      case PAddrBits => 32
-      case VAddrBits => 43
-      case PgIdxBits => 13
-      case ASIdBits => 7
-      case PermBits => 6
-      case PPNBits => here(PAddrBits) - here(PgIdxBits)
-      case VPNBits => here(VAddrBits) - here(PgIdxBits)
-      case MIFTagBits => 5
-      case MIFDataBits => 128
-      case MIFAddrBits => here(PAddrBits) - here[Int]("OFFSET_BITS")
-      case MIFDataBeats => 4
-      //Uncore Constants
-      case TileLinkL1Params => Alter({
-          case LNMasters => site[Int]("NBANKS")
-          case LNClients => site[Int]("NTILES")+1
-          case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients)
-          case TLCoherence => site(Coherence)
-          case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS")
-          case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS"))
-          case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1)
-          case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8
-          case TLWriteMaskBits => 6
-          case TLWordAddrBits  => 3
-          case TLAtomicOpBits  => 4
-        })
-      case L2HellaCacheParams => Alter({
-          case NReleaseTransactors =>  site[Int]("NL2_REL_XACTS")
-          case NAcquireTransactors =>  site[Int]("NL2_ACQ_XACTS")
-          case NClients => site[Int]("NTILES") + 1
-          case NSets => 512
-          case NWays => 8
-          case BlockOffBits => 0
-          case RowBits => site(TLDataBits)
-          case WordBits => site(XprLen)
-          case Replacer => () => new RandomReplacement(8)//site(NWays))
-        })
-      case NTiles => here[Int]("NTILES")
-      case NBanks => here[Int]("NBANKS")
-      case BankIdLSB => 5
-      case BuildDRAMSideLLC => () => {
-        val refill = site(TLDataBits)/site(MIFDataBits)
-        if(site[Boolean]("USE_DRAMSIDE_LLC")) {
-          val tag = Mem(Bits(width = 152), 512, seqRead = true)
-          val data = Mem(Bits(width = 64), 4096, seqRead = true)
-          Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, 
-            refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
-        } else { Module(new DRAMSideLLCNull(16, refill)) }
-      }
-      case BuildCoherentMaster => (id: Int, p: Some[Parameters]) => {
-        if(!site[Boolean]("USE_DRAMSIDE_LLC")) { 
-          Module(new L2CoherenceAgent(id))(p)
-        } else {
-          Module(new L2HellaCache(id))(p)
-        }
-      }
-      //HTIF Constants
-      case HTIFWidth => 16
-      case HTIFNSCR => 64
-      case HTIFOffsetBits => here[Int]("OFFSET_BITS")
-      case HTIFNCores => here[Int]("NTILES")
-    }
-  }
-}
-
 case object NTiles extends Field[Int]
 case object NBanks extends Field[Int]
 case object BankIdLSB extends Field[Int]
-case object TileLinkL1Params extends Field[PF]
+case object CacheBlockBytes extends Field[Int]
-case object L2HellaCacheParams extends Field[PF]
+case object CacheBlockOffsetBits extends Field[Int]
 case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike]
-case object BuildCoherentMaster extends Field[(Int,Option[Parameters]) => CoherenceAgent]
+case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent]
 case object Coherence extends Field[CoherencePolicyWithUncached]
 
 class OuterMemorySystem extends Module
@@ -174,10 +27,9 @@ class OuterMemorySystem extends Module
 
   val refill_cycles = params(TLDataBits)/params(MIFDataBits)
   val llc = params(BuildDRAMSideLLC)()
-  val l2p = Some(params.alter(params(L2HellaCacheParams)))
+  val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster))
-  val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)(_,l2p))
 
-  val net = Module(new ReferenceChipCrossbarNetwork)(l2p)
+  val net = Module(new ReferenceChipCrossbarNetwork)
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
   masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
@@ -310,13 +162,12 @@ class Top extends Module {
   //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
   //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
 
-  val nTiles = params[Int]("NTILES")
+  val nTiles = params(NTiles)
   val io = new VLSITopIO
 
-  val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?
   val resetSigs = Vec.fill(nTiles){Bool()}
-  val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient?
+  val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
-  val uncore = Module(new Uncore, tl)
+  val uncore = Module(new Uncore)
 
   for (i <- 0 until nTiles) {
     val hl = uncore.io.htif(i)

src/main/scala/fpga.scala

@@ -14,7 +14,7 @@ class FPGAOuterMemorySystem extends Module {
     val mem = new MemIO
   }
 
-  val master = Module(new L2CoherenceAgent(0), params(L2HellaCacheParams))
+  val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"})
   val net = Module(new ReferenceChipCrossbarNetwork)
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters.head <> master.io.inner
@@ -88,8 +88,6 @@ class FPGATop extends Module {
   val nTiles = params(NTiles)
   val io = new FPGATopIO
  
-  params.alter(params(TileLinkL1Params))
-
   val resetSigs = Vec.fill(nTiles){Bool()}
   val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
   val uncore = Module(new FPGAUncore)

uncore

@@ -1 +1 @@
-Subproject commit 37fdf25582b9c0ef48dceecb76416c955f0bc81e
+Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5