tilelink2 Atomics: optimize the sign-extension circuit
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@ -36,6 +36,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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val managers = edgeOut.manager.managers
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val beatBytes = edgeOut.manager.beatBytes
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// To which managers are we adding atomic support?
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val ourSupport = TransferSizes(1, edgeOut.manager.beatBytes)
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@ -122,26 +123,29 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
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val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
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// Logical AMO
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val lut = Vec(a_cam_a.lut.toBools)
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val indexes = (a_a.toBools zip a_d.toBools) map { case (a,d) => a.asUInt << 1 | d.asUInt }
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val logic_out = Cat(indexes.map(x => lut(x).asUInt).reverse)
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val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
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val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
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// Arithmetic AMO
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val unsigned = a_cam_a.bits.param(1)
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val take_max = a_cam_a.bits.param(0)
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val adder = a_cam_a.bits.param(2)
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val mask = FillInterleaved(8, a_cam_a.bits.mask)
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val signBit = ~(~mask | (mask >> 1))
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val sign_a = a_a & signBit
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val sign_d = a_d & signBit
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val signext_a = Vec(sign_a.toBools.scanLeft(Bool(false))(_||_).init).asUInt
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val signext_d = Vec(sign_d.toBools.scanLeft(Bool(false))(_||_).init).asUInt
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val mask = a_cam_a.bits.mask
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val signSel = ~(~mask | (mask >> 1))
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val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
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val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
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// Move the selected sign bit into the first byte position it will extend
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val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
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val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
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val signext_a = FillInterleaved(8, highOR(signbit_a))
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val signext_d = FillInterleaved(8, highOR(signbit_d))
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// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
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val a_a_ext = (a_a & mask) | signext_a
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val a_d_ext = (a_d & mask) | signext_d
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val wide_mask = FillInterleaved(8, mask)
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val a_a_ext = (a_a & wide_mask) | signext_a
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val a_d_ext = (a_d & wide_mask) | signext_d
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val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
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val adder_out = a_a_ext + a_d_inv
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val h = 8*edgeOut.manager.beatBytes-1 // now sign-extended; use biggest bit
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val h = 8*beatBytes-1 // now sign-extended; use biggest bit
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val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
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val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
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val pick_a = take_max === a_bigger
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@ -13,7 +13,7 @@ package object tilelink2
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def highOR(x: UInt) = {
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val w = x.getWidth
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def helper(s: Int, x: UInt): UInt =
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if (s >= w) x else helper(s+s, x | x << s)
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if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
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helper(1, x)
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}
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