rocketchip: add Zero device to the memory subsystem

src/main/scala/rocketchip/Configs.scala

@@ -31,6 +31,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
   case PeripheryBusArithmetic => true
   // Note that PLIC asserts that this is > 0.
   case IncludeJtagDTM => false
+  case ZeroConfig => ZeroConfig(base=0xa000000L, size=0x2000000L, beatBytes=8)
   case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
   case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
   case ExtIn  => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
@@ -86,6 +87,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
 
 class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
   case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
+  case ZeroConfig => up(ZeroConfig, site).copy(beatBytes = dataBits/8)
 })
 
 class Edge128BitConfig extends Config(

src/main/scala/rocketchip/ExampleTop.scala

@@ -30,6 +30,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _
 
 class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
     with PeripheryBootROM
+    with PeripheryZero
     with PeripheryDebug
     with PeripheryCounter
     with HardwiredResetVector
@@ -39,6 +40,7 @@ class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
 
 class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
     with PeripheryBootROMBundle
+    with PeripheryZeroBundle
     with PeripheryDebugBundle
     with PeripheryCounterBundle
     with HardwiredResetVectorBundle
@@ -46,6 +48,7 @@ class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleT
 
 class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
     with PeripheryBootROMModule
+    with PeripheryZeroModule
     with PeripheryDebugModule
     with PeripheryCounterModule
     with HardwiredResetVectorModule

src/main/scala/rocketchip/Periphery.scala

@@ -34,6 +34,9 @@ case object PeripheryBusConfig extends Field[TLBusConfig]
 case object PeripheryBusArithmetic extends Field[Boolean]
 /* Specifies the SOC-bus configuration */
 case object SOCBusConfig extends Field[TLBusConfig]
+/* Specifies the location of the Zero device */
+case class ZeroConfig(base: Long, size: Long, beatBytes: Int)
+case object ZeroConfig extends Field[ZeroConfig]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasPeripheryParameters {
@@ -121,6 +124,36 @@ trait PeripheryMasterAXI4MemModule {
 
 /////
 
+trait PeripheryZero {
+  this: TopNetwork =>
+  val module: PeripheryZeroModule
+
+  private val config = p(ZeroConfig)
+  private val address = AddressSet(config.base, config.size-1)
+  private val lineBytes = p(CacheBlockBytes)
+
+  val zeros = mem map { case xbar =>
+    val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
+    zero.node := TLFragmenter(config.beatBytes, lineBytes)(xbar.node)
+    zero
+  }
+}
+
+trait PeripheryZeroBundle {
+  this: TopNetworkBundle {
+    val outer: PeripheryZero
+  } =>
+}
+
+trait PeripheryZeroModule {
+  this: TopNetworkModule {
+    val outer: PeripheryZero
+    val io: PeripheryZeroBundle
+  } =>
+}
+
+/////
+
 // PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
 trait PeripheryMasterAXI4MMIO {
   this: TopNetwork =>