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rocketchip: add Zero device to the memory subsystem

This commit is contained in:
Wesley W. Terpstra 2017-02-03 17:18:20 -08:00
parent b240505a15
commit a3e56cfa5e
3 changed files with 38 additions and 0 deletions

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@ -31,6 +31,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
case PeripheryBusArithmetic => true case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0. // Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false case IncludeJtagDTM => false
case ZeroConfig => ZeroConfig(base=0xa000000L, size=0x2000000L, beatBytes=8)
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4) case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4) case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2) case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
@ -86,6 +87,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => { class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8) case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
case ZeroConfig => up(ZeroConfig, site).copy(beatBytes = dataBits/8)
}) })
class Edge128BitConfig extends Config( class Edge128BitConfig extends Config(

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@ -30,6 +30,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _
class ExampleRocketTop(implicit p: Parameters) extends ExampleTop class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
with PeripheryBootROM with PeripheryBootROM
with PeripheryZero
with PeripheryDebug with PeripheryDebug
with PeripheryCounter with PeripheryCounter
with HardwiredResetVector with HardwiredResetVector
@ -39,6 +40,7 @@ class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer) class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle with PeripheryBootROMBundle
with PeripheryZeroBundle
with PeripheryDebugBundle with PeripheryDebugBundle
with PeripheryCounterBundle with PeripheryCounterBundle
with HardwiredResetVectorBundle with HardwiredResetVectorBundle
@ -46,6 +48,7 @@ class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleT
class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule with PeripheryBootROMModule
with PeripheryZeroModule
with PeripheryDebugModule with PeripheryDebugModule
with PeripheryCounterModule with PeripheryCounterModule
with HardwiredResetVectorModule with HardwiredResetVectorModule

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@ -34,6 +34,9 @@ case object PeripheryBusConfig extends Field[TLBusConfig]
case object PeripheryBusArithmetic extends Field[Boolean] case object PeripheryBusArithmetic extends Field[Boolean]
/* Specifies the SOC-bus configuration */ /* Specifies the SOC-bus configuration */
case object SOCBusConfig extends Field[TLBusConfig] case object SOCBusConfig extends Field[TLBusConfig]
/* Specifies the location of the Zero device */
case class ZeroConfig(base: Long, size: Long, beatBytes: Int)
case object ZeroConfig extends Field[ZeroConfig]
/** Utility trait for quick access to some relevant parameters */ /** Utility trait for quick access to some relevant parameters */
trait HasPeripheryParameters { trait HasPeripheryParameters {
@ -121,6 +124,36 @@ trait PeripheryMasterAXI4MemModule {
///// /////
trait PeripheryZero {
this: TopNetwork =>
val module: PeripheryZeroModule
private val config = p(ZeroConfig)
private val address = AddressSet(config.base, config.size-1)
private val lineBytes = p(CacheBlockBytes)
val zeros = mem map { case xbar =>
val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
zero.node := TLFragmenter(config.beatBytes, lineBytes)(xbar.node)
zero
}
}
trait PeripheryZeroBundle {
this: TopNetworkBundle {
val outer: PeripheryZero
} =>
}
trait PeripheryZeroModule {
this: TopNetworkModule {
val outer: PeripheryZero
val io: PeripheryZeroBundle
} =>
}
/////
// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one. // PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
trait PeripheryMasterAXI4MMIO { trait PeripheryMasterAXI4MMIO {
this: TopNetwork => this: TopNetwork =>