riscv/rocket-chip
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rocketchip: add Zero device to the memory subsystem

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This commit is contained in:
Wesley W. Terpstra
2017-02-03 17:18:20 -08:00
parent b240505a15
commit a3e56cfa5e
3 changed files with 38 additions and 0 deletions
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3
src/main/scala/rocketchip/ExampleTop.scala
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@ -30,6 +30,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _
class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
with PeripheryBootROM
with PeripheryZero
with PeripheryDebug
with PeripheryCounter
with HardwiredResetVector
@ -39,6 +40,7 @@ class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryZeroBundle
with PeripheryDebugBundle
with PeripheryCounterBundle
with HardwiredResetVectorBundle
@ -46,6 +48,7 @@ class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleT
class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryZeroModule
with PeripheryDebugModule
with PeripheryCounterModule
with HardwiredResetVectorModule