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synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive

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This commit is contained in:
Megan Wachs 2017-08-30 12:59:16 -07:00
parent 8139014c9e
commit a3bc5f2e33
1 changed files with 37 additions and 19 deletions
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56
src/main/scala/util/SynchronizingReg.scala
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@ -12,12 +12,16 @@ import Chisel._
* rather than buffering. * rather than buffering.
* *
* The 3 different types vary in their reset behavior: * The 3 different types vary in their reset behavior:
* AsyncResetShiftReg -- This is identical to the AsyncResetSynchronizerShiftReg,
* it is just named differently
* to distinguish its use case. This is a ShiftRegister meant for timing,
* not for synchronization.
* AsyncResetSynchronizerShiftReg -- asynchronously reset to 0 * AsyncResetSynchronizerShiftReg -- asynchronously reset to 0
* SynchronizerShiftReg -- no reset, pipeline only. * SynchronizerShiftReg -- no reset, pipeline only.
* *
*/ */
abstract class AbstractSynchronizerReg(w: Int = 1) extends Module { abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = new Bundle { val io = new Bundle {
val d = UInt(INPUT, width = w) val d = UInt(INPUT, width = w)
@ -26,43 +30,57 @@ abstract class AbstractSynchronizerReg(w: Int = 1) extends Module {
} }
object AbstractSynchronizerReg { object AbstractPipelineReg {
def apply [T <: Chisel.Data](gen: => AbstractSynchronizerReg, in: T, name: Option[String] = None): T = { def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val sync_chain = Module(gen) val chain = Module(gen)
name.foreach{ sync_chain.suggestName(_) } name.foreach{ chain.suggestName(_) }
sync_chain.io.d := in.asUInt chain.io.d := in.asUInt
sync_chain.io.q.asTypeOf(in) chain.io.q.asTypeOf(in)
} }
} }
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) { class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(sync > 0, "Sync must be greater than 0.") require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}" override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val syncv = List.tabulate(sync) { i => val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, 0)).suggestName(s"sync_${i}") Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
} }
syncv.last.io.d := io.d chain.last.io.d := io.d
syncv.last.io.en := Bool(true) chain.last.io.en := Bool(true)
(syncv.init zip syncv.tail).foreach { case (sink, source) => (chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q sink.io.d := source.io.q
sink.io.en := Bool(true) sink.io.en := Bool(true)
} }
io.q := syncv.head.io.q io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
AbstractPipelineReg(gen = {new AsyncResetShiftReg(in.getWidth, depth, init)}, in, name)
}
//Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
// not try to merge instances of this with instances of the superclass.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncResetShiftReg(w, depth = sync, name = "sync") {
require(sync > 0, "Sync must be greater than 0.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}"
} }
object AsyncResetSynchronizerShiftReg { object AsyncResetSynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractSynchronizerReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name) AbstractPipelineReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name)
} }
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchronizerReg(w) { class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 0, "Sync must be greater than 0.") require(sync > 0, "Sync must be greater than 0.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
@ -84,5 +102,5 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractSynchroniz
object SynchronizerShiftReg { object SynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractSynchronizerReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name) AbstractPipelineReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name)
} }