Fix priority inversion for two back-to-back divides (#948)
If the first one is killed for some unrelated reason (e.g. write port hazard), the second one will still issue to the div-sqrt unit. While it will itself later be killed, the fact that the later instruction acquires a resource needed by the former instruction leads to deadlock.
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@ -581,12 +581,17 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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val req_valid = ex_reg_valid || io.cp_req.valid
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val req_valid = ex_reg_valid || io.cp_req.valid
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val ex_reg_inst = RegEnable(io.inst, io.valid)
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val ex_reg_inst = RegEnable(io.inst, io.valid)
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val ex_cp_valid = io.cp_req.fire()
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val ex_cp_valid = io.cp_req.fire()
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val mem_reg_valid = Reg(next=ex_reg_valid && !io.killx || ex_cp_valid, init=Bool(false))
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val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
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val mem_cp_valid = Reg(next=ex_cp_valid, init=Bool(false))
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val mem_cp_valid = Reg(next=ex_cp_valid, init=Bool(false))
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val killm = (io.killm || io.nack_mem) && !mem_cp_valid
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val wb_reg_valid = Reg(next=mem_reg_valid && (!killm || mem_cp_valid), init=Bool(false))
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val wb_cp_valid = Reg(next=mem_cp_valid, init=Bool(false))
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val wb_cp_valid = Reg(next=mem_cp_valid, init=Bool(false))
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val mem_reg_valid = RegInit(false.B)
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val killm = (io.killm || io.nack_mem) && !mem_cp_valid
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// Kill X-stage instruction if M-stage is killed. This prevents it from
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// speculatively being sent to the div-sqrt unit, which can cause priority
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// inversion for two back-to-back divides, the first of which is killed.
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val killx = io.killx || mem_reg_valid && killm
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mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
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val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
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val wb_reg_valid = Reg(next=mem_reg_valid && (!killm || mem_cp_valid), init=Bool(false))
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val fp_decoder = Module(new FPUDecoder)
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val fp_decoder = Module(new FPUDecoder)
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fp_decoder.io.inst := io.inst
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fp_decoder.io.inst := io.inst
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