riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

soc: compatible with "simple-bus" => scanned for platform devices

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-03-29 23:50:58 -07:00 committed by Andrew Waterman
parent 9f85b2e996
commit a2fc51d65e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/CoreplexNetwork.scala
View File

@ -66,7 +66,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
Description("soc", Map( Description("soc", Map(
"#address-cells" -> width, "#address-cells" -> width,
"#size-cells" -> width, "#size-cells" -> width,
"compatible" -> (p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")), "compatible" -> ((p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")) :+ ResourceString("simple-bus")),
"ranges" -> Nil)) "ranges" -> Nil))
} }
} }