riscv/rocket-chip
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Error grants (#1025)

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* CacheCork: an error Grant still says 'toT' even though it is transient

Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.

This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.

* Error: handle permissions properly
This commit is contained in:
Wesley W. Terpstra 2017-10-02 14:49:25 -07:00 committed by GitHub
parent 723af5e6b6
commit a2dc13669a
2 changed files with 3 additions and 6 deletions
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4
src/main/scala/devices/tilelink/Error.scala
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@ -59,7 +59,7 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant) val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant)
da.bits.opcode := a_opcodes(a.bits.opcode) da.bits.opcode := a_opcodes(a.bits.opcode)
da.bits.param := UInt(0) da.bits.param := UInt(0) // toT, but error grants must be handled transiently (ie: you don't keep permissions)
da.bits.size := a.bits.size da.bits.size := a.bits.size
da.bits.source := a.bits.source da.bits.source := a.bits.source
da.bits.sink := UInt(0) da.bits.sink := UInt(0)
@ -70,7 +70,7 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) e
dc.valid := c.valid && c_last dc.valid := c.valid && c_last
dc.bits.opcode := ReleaseAck dc.bits.opcode := ReleaseAck
dc.bits.param := Vec(toN, toN, toB)(c.bits.param) dc.bits.param := Vec(toB, toN, toN)(c.bits.param)
dc.bits.size := c.bits.size dc.bits.size := c.bits.size
dc.bits.source := c.bits.source dc.bits.source := c.bits.source
dc.bits.sink := UInt(0) dc.bits.sink := UInt(0)

5
src/main/scala/tilelink/CacheCork.scala
View File

@ -100,10 +100,7 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) { when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) {
d_d.bits.opcode := GrantData d_d.bits.opcode := GrantData
// On Grant error, you do NOT get the permissions you asked for. d_d.bits.param := TLPermissions.toT
// We only enter this case from NtoT or NtoB, so that means use toN.
// (the BtoT case was handled by a_d)
d_d.bits.param := Mux(out.d.bits.error, TLPermissions.toN, TLPermissions.toT)
} }
when (out.d.bits.opcode === AccessAck && !out.d.bits.source(0)) { when (out.d.bits.opcode === AccessAck && !out.d.bits.source(0)) {
d_d.bits.opcode := ReleaseAck d_d.bits.opcode := ReleaseAck