riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add VM covers

Browse Source
This commit is contained in:
Andrew Waterman
2018-01-23 16:13:35 -08:00
parent dcda98dcaf
commit a2ca82f92c
1 changed files with 9 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/main/scala/rocket/PTW.scala
View File

@@ -279,6 +279,15 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
count := pgLevels-1
}
for (i <- 0 until pgLevels) {
val leaf = io.mem.resp.valid && !traverse && count === i
ccover(leaf && pte.v && !invalid_paddr, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && !io.mem.resp.bits.data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && io.mem.resp.bits.data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(io.mem.resp.valid && count === pgLevels-1 && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")