riscv/rocket-chip
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Allow ICacheConfig to toggle fetch-width.

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This commit is contained in:
Christopher Celio 2014-01-22 16:19:57 -08:00
parent a7489920ce
commit a2be21361e
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/icache.scala
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@ -5,11 +5,11 @@ import uncore._
import Util._ import Util._
case class ICacheConfig(sets: Int, assoc: Int, case class ICacheConfig(sets: Int, assoc: Int,
ibytes: Int = 4,
ntlb: Int = 8, nbtb: Int = 8, ntlb: Int = 8, nbtb: Int = 8,
code: Code = new IdentityCode) code: Code = new IdentityCode)
{ {
val w = 1 val w = 1
val ibytes = 4
val dm = assoc == 1 val dm = assoc == 1
val lines = sets * assoc val lines = sets * assoc