riscv/rocket-chip
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diplomacy: move rendering properties to edges

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FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
This commit is contained in:
Wesley W. Terpstra
2017-09-26 13:23:54 -07:00
parent 76c2aa1661
commit a27e853101
10 changed files with 59 additions and 78 deletions
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26
src/main/scala/tile/RocketTile.scala
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@ -199,13 +199,13 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
}
}
def optionalSlaveBuffer(in: TLOutwardNode): TLOutwardNode = {
def optionalSlaveBuffer(out: TLInwardNode): TLInwardNode = {
if (rtp.boundaryBuffers) {
val sbuf = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
DisableMonitors { implicit p => sbuf.node :*= in }
DisableMonitors { implicit p => out :*= sbuf.node }
sbuf.node
} else {
in
out
}
}
@ -234,9 +234,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = optionalMasterBuffer(rocket.masterNode)
val slaveNode = new TLIdentityNode() { override def reverse = true }
DisableMonitors { implicit p => rocket.slaveNode :*= optionalSlaveBuffer(slaveNode) }
val slaveNode = optionalSlaveBuffer(rocket.slaveNode)
// Fully async interrupts need synchronizers.
// Others need no synchronization.
@ -259,13 +257,9 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
source.node :=* rocket.masterNode
val masterNode = source.node
val slaveNode = new TLAsyncIdentityNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
DisableMonitors { implicit p =>
rocket.slaveNode :*= sink.node
sink.node :*= slaveNode
}
DisableMonitors { implicit p => rocket.slaveNode :*= sink.node }
val slaveNode = sink.node
// Fully async interrupts need synchronizers,
// as do those coming from the periphery clock.
@ -289,13 +283,9 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
source.node :=* optionalMasterBuffer(rocket.masterNode)
val masterNode = source.node
val slaveNode = new TLRationalIdentityNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
DisableMonitors { implicit p =>
sink.node :*= slaveNode
rocket.slaveNode :*= optionalSlaveBuffer(sink.node)
}
DisableMonitors { implicit p => optionalSlaveBuffer(rocket.slaveNode) :*= sink.node }
val slaveNode = sink.node
// Fully async interrupts need synchronizers.
// Those coming from periphery clock need a