riscv/rocket-chip
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RoCC PTW refactoring

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This commit is contained in:
Yunsup Lee 2016-02-24 22:52:02 -08:00
parent ef4915bd2c
commit a2381d2faf
2 changed files with 5 additions and 2 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 6c0e1caaf535ab8cf24368e0d023ef36c35a3ccd
Subproject commit abda4649cf353a8dca1fdd2cc536cb015a6237b3

5
src/main/scala/Configs.scala
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@ -153,6 +153,7 @@ class DefaultConfig extends Config (
}
case BuildRoCC => Nil
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
case UseDma => false
case UseStreamLoopback => false
@ -396,7 +397,8 @@ class WithRoccExample extends Config(
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
RoccParameters(
opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => Module(new TranslatorExample()(p))),
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
nPTWPorts = 1),
RoccParameters(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
@ -413,6 +415,7 @@ class WithDmaController extends Config(
RoccParameters(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new DmaController()(p)),
nPTWPorts = 1,
csrs = Seq.range(
DmaCtrlRegNumbers.CSR_BASE,
DmaCtrlRegNumbers.CSR_END)))