riscv/rocket-chip
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Bits -> UInt

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This commit is contained in:
Andrew Waterman 2015-08-03 18:01:06 -07:00
parent 9c7a41e8d3
commit a21979a2fa
2 changed files with 14 additions and 14 deletions
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26
uncore/src/main/scala/ecc.scala
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@ -6,8 +6,8 @@ import Chisel._
abstract class Decoding abstract class Decoding
{ {
def uncorrected: Bits def uncorrected: UInt
def corrected: Bits def corrected: UInt
def correctable: Bool def correctable: Bool
def uncorrectable: Bool def uncorrectable: Bool
def error = correctable || uncorrectable def error = correctable || uncorrectable
@ -16,15 +16,15 @@ abstract class Decoding
abstract class Code abstract class Code
{ {
def width(w0: Int): Int def width(w0: Int): Int
def encode(x: Bits): Bits def encode(x: UInt): UInt
def decode(x: Bits): Decoding def decode(x: UInt): Decoding
} }
class IdentityCode extends Code class IdentityCode extends Code
{ {
def width(w0: Int) = w0 def width(w0: Int) = w0
def encode(x: Bits) = x def encode(x: UInt) = x
def decode(y: Bits) = new Decoding { def decode(y: UInt) = new Decoding {
def uncorrected = y def uncorrected = y
def corrected = y def corrected = y
def correctable = Bool(false) def correctable = Bool(false)
@ -35,8 +35,8 @@ class IdentityCode extends Code
class ParityCode extends Code class ParityCode extends Code
{ {
def width(w0: Int) = w0+1 def width(w0: Int) = w0+1
def encode(x: Bits) = Cat(x.xorR, x) def encode(x: UInt) = Cat(x.xorR, x)
def decode(y: Bits) = new Decoding { def decode(y: UInt) = new Decoding {
def uncorrected = y(y.getWidth-2,0) def uncorrected = y(y.getWidth-2,0)
def corrected = uncorrected def corrected = uncorrected
def correctable = Bool(false) def correctable = Bool(false)
@ -50,7 +50,7 @@ class SECCode extends Code
val m = new Unsigned(k).log2 + 1 val m = new Unsigned(k).log2 + 1
k + m + (if((1 << m) < m+k+1) 1 else 0) k + m + (if((1 << m) < m+k+1) 1 else 0)
} }
def encode(x: Bits) = { def encode(x: UInt) = {
val k = x.getWidth val k = x.getWidth
require(k > 0) require(k > 0)
val n = width(k) val n = width(k)
@ -65,7 +65,7 @@ class SECCode extends Code
} }
Vec(y).toBits Vec(y).toBits
} }
def decode(y: Bits) = new Decoding { def decode(y: UInt) = new Decoding {
val n = y.getWidth val n = y.getWidth
require(n > 0 && !isPow2(n)) require(n > 0 && !isPow2(n))
@ -77,7 +77,7 @@ class SECCode extends Code
} }
val s = Vec(syndrome).toBits val s = Vec(syndrome).toBits
private def swizzle(z: Bits) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
def uncorrected = swizzle(y) def uncorrected = swizzle(y)
def corrected = swizzle(((y.toUInt << UInt(1)) ^ UIntToOH(s)) >> UInt(1)) def corrected = swizzle(((y.toUInt << UInt(1)) ^ UIntToOH(s)) >> UInt(1))
def correctable = s.orR def correctable = s.orR
@ -92,8 +92,8 @@ class SECDEDCode extends Code
private val par = new ParityCode private val par = new ParityCode
def width(k: Int) = sec.width(k)+1 def width(k: Int) = sec.width(k)+1
def encode(x: Bits) = par.encode(sec.encode(x)) def encode(x: UInt) = par.encode(sec.encode(x))
def decode(x: Bits) = new Decoding { def decode(x: UInt) = new Decoding {
val secdec = sec.decode(x(x.getWidth-2,0)) val secdec = sec.decode(x(x.getWidth-2,0))
val pardec = par.decode(x) val pardec = par.decode(x)

2
uncore/src/main/scala/htif.scala
View File

@ -256,7 +256,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
io.scr.wen := Bool(false) io.scr.wen := Bool(false)
io.scr.wdata := pcr_wdata io.scr.wdata := pcr_wdata
io.scr.waddr := scr_addr.toUInt io.scr.waddr := scr_addr.toUInt
when (state === state_pcr_req && pcr_coreid === SInt(-1)) { when (state === state_pcr_req && pcr_coreid.andR) {
io.scr.wen := cmd === cmd_writecr io.scr.wen := cmd === cmd_writecr
pcrReadData := scr_rdata(scr_addr) pcrReadData := scr_rdata(scr_addr)
state := state_tx state := state_tx