Headerless TileLinkIO and arbiters
This commit is contained in:
Henry Cook
@ -3,6 +3,7 @@
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package uncore
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import Chisel._
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import scala.math.max
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import scala.reflect.ClassTag
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// Parameters exposed to the top-level design, set based on
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// external requirements or design space exploration
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@ -290,7 +291,6 @@ object Probe {
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}
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}
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class Release extends ClientToManagerChannel
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with HasCacheBlockAddress
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with HasClientTransactionId
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@ -420,6 +420,42 @@ object TileLinkIOWrapper {
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def apply(tl: TileLinkIO) = tl
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}
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// This version of TileLinkIO does not contain network headers for packets
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// that originate in the Clients (i.e. Acquire and Release). These headers
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// are provided in the top-level that instantiates the clients and network.
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// By eliding the header subbundles within the clients we can enable
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// hierarchical P&R while minimizing unconnected port errors in GDS.
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class HeaderlessUncachedTileLinkIO extends TLBundle {
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val acquire = new DecoupledIO(new Acquire)
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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}
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class HeaderlessTileLinkIO extends HeaderlessUncachedTileLinkIO {
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val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
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val release = new DecoupledIO(new Release)
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}
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class HeaderlessTileLinkIOWrapper extends TLModule {
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val io = new Bundle {
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val in = new HeaderlessUncachedTileLinkIO().flip
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val out = new HeaderlessTileLinkIO
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}
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io.out.acquire <> io.in.acquire
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io.out.grant <> io.in.grant
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io.out.finish <> io.in.finish
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io.out.probe.ready := Bool(false)
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io.out.release.valid := Bool(false)
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}
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object HeaderlessTileLinkIOWrapper {
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def apply(utl: HeaderlessUncachedTileLinkIO): HeaderlessTileLinkIO = {
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val conv = Module(new HeaderlessTileLinkIOWrapper)
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conv.io.in <> utl
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conv.io.out
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}
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}
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abstract trait HasArbiterTypes {
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val arbN: Int
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type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
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@ -428,6 +464,7 @@ abstract trait HasArbiterTypes {
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HasClientTransactionId with
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HasTileLinkData
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}
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// Utility functions for constructing TileLinkIO arbiters
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abstract class TileLinkArbiterLike(val arbN: Int) extends TLModule
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with HasArbiterTypes {
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@ -438,34 +475,65 @@ abstract class TileLinkArbiterLike(val arbN: Int) extends TLModule
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def managerSourcedClientXactId(in: ManagerSourcedWithId): Bits
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def arbIdx(in: ManagerSourcedWithId): UInt
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def hookupClientSource[M <: ClientSourcedWithIdAndData]
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(ins: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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out: DecoupledIO[LogicalNetworkIO[M]]) {
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def hookupClientSource[M <: ClientSourcedWithIdAndData : ClassTag]
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(clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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mngr: DecoupledIO[LogicalNetworkIO[M]]) {
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def hasData(m: LogicalNetworkIO[M]) = m.payload.hasMultibeatData()
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val arb = Module(new LockingRRArbiter(out.bits.clone, arbN, params(TLDataBeats), Some(hasData _)))
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out <> arb.io.out
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ins.zipWithIndex.zip(arb.io.in).map{ case ((req,id), arb) => {
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val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, params(TLDataBeats), Some(hasData _)))
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clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
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arb.valid := req.valid
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arb.bits := req.bits
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arb.bits.payload.client_xact_id := clientSourcedClientXactId(req.bits.payload, id)
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req.ready := arb.ready
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}}
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arb.io.out <> mngr
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}
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def hookupManagerSource[M <: ManagerSourcedWithId]
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(ins: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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out: DecoupledIO[LogicalNetworkIO[M]]) {
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out.ready := Bool(false)
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def hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData : ClassTag]
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(clts: Seq[DecoupledIO[M]],
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mngr: DecoupledIO[M]) {
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def hasData(m: M) = m.hasMultibeatData()
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val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, params(TLDataBeats), Some(hasData _)))
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clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
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arb.valid := req.valid
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arb.bits := req.bits
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arb.bits.client_xact_id := clientSourcedClientXactId(req.bits, id)
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req.ready := arb.ready
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}}
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arb.io.out <> mngr
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}
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def hookupFinish[M <: LogicalNetworkIO[Finish] : ClassTag]
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(clts: Seq[DecoupledIO[M]],
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mngr: DecoupledIO[M]) {
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val arb = Module(new RRArbiter(mngr.bits.clone, arbN))
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arb.io.in zip clts map { case (arb, req) => arb <> req }
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arb.io.out <> mngr
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}
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def hookupManagerSourceWithId[M <: ManagerSourcedWithId]
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(clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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mngr: DecoupledIO[LogicalNetworkIO[M]]) {
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mngr.ready := Bool(false)
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for (i <- 0 until arbN) {
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ins(i).valid := Bool(false)
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when (arbIdx(out.bits.payload) === UInt(i)) {
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ins(i).valid := out.valid
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out.ready := ins(i).ready
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clts(i).valid := Bool(false)
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when (arbIdx(mngr.bits.payload) === UInt(i)) {
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clts(i).valid := mngr.valid
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mngr.ready := clts(i).ready
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}
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ins(i).bits := out.bits
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ins(i).bits.payload.client_xact_id := managerSourcedClientXactId(out.bits.payload)
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clts(i).bits := mngr.bits
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clts(i).bits.payload.client_xact_id :=
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managerSourcedClientXactId(mngr.bits.payload)
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}
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}
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def hookupManagerSourceBroadcast[M <: ManagerToClientChannel]
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(clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
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mngr: DecoupledIO[LogicalNetworkIO[M]]) {
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clts.map{ _.valid := mngr.valid }
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clts.map{ _.bits := mngr.bits }
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mngr.ready := clts.map(_.ready).reduce(_||_)
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}
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}
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abstract class UncachedTileLinkIOArbiter(n: Int)
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@ -474,13 +542,9 @@ abstract class UncachedTileLinkIOArbiter(n: Int)
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val in = Vec.fill(n){new UncachedTileLinkIO}.flip
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val out = new UncachedTileLinkIO
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}
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hookupClientSource(io.in.map(_.acquire), io.out.acquire)
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hookupManagerSource(io.in.map(_.grant), io.out.grant)
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val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
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io.out.finish <> finish_arb.io.out
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finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
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hookupFinish(io.in.map(_.finish), io.out.finish)
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hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
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}
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abstract class TileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n) {
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@ -488,18 +552,11 @@ abstract class TileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n) {
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val in = Vec.fill(n){new TileLinkIO}.flip
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val out = new TileLinkIO
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}
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hookupClientSource(io.in.map(_.acquire), io.out.acquire)
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hookupClientSource(io.in.map(_.release), io.out.release)
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hookupManagerSource(io.in.map(_.grant), io.out.grant)
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io.in.map{ _.probe.valid := io.out.probe.valid }
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io.in.map{ _.probe.bits := io.out.probe.bits }
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io.out.probe.ready := io.in.map(_.probe.ready).reduce(_||_)
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val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
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io.out.finish <> finish_arb.io.out
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finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
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hookupFinish(io.in.map(_.finish), io.out.finish)
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hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
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hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
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}
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// Appends the port index of the arbiter to the client_xact_id
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