parent
31b72625aa
commit
a1ebc73477
@ -358,13 +358,25 @@ object Acquire {
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operand_size: UInt,
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operand_size: UInt,
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opcode: UInt,
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opcode: UInt,
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wmask: UInt,
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wmask: UInt,
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alloc: Bool): UInt = {
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alloc: Bool)
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(implicit p: Parameters): UInt = {
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val tlExternal = p(TLKey(p(TLId)))
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val tlWriteMaskBits = tlExternal.writeMaskBits
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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// These had better be the right size when we cat them together!
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val my_addr_byte = (UInt(0, tlByteAddrBits) | addr_byte)(tlByteAddrBits-1, 0)
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val my_operand_size = (UInt(0, MT_SZ) | operand_size)(MT_SZ-1, 0)
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val my_opcode = (UInt(0, M_SZ) | opcode)(M_SZ-1, 0)
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val my_wmask = (UInt(0, tlWriteMaskBits) | wmask)(tlWriteMaskBits-1, 0)
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MuxLookup(a_type, UInt(0), Array(
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MuxLookup(a_type, UInt(0), Array(
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Acquire.getType -> Cat(addr_byte, operand_size, opcode, alloc),
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Acquire.getType -> Cat(my_addr_byte, my_operand_size, my_opcode, alloc),
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Acquire.getBlockType -> Cat(operand_size, opcode, alloc),
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Acquire.getBlockType -> Cat(my_operand_size, my_opcode, alloc),
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Acquire.putType -> Cat(wmask, alloc),
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Acquire.putType -> Cat(my_wmask, alloc),
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Acquire.putBlockType -> Cat(wmask, alloc),
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Acquire.putBlockType -> Cat(my_wmask, alloc),
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Acquire.putAtomicType -> Cat(addr_byte, operand_size, opcode, alloc),
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Acquire.putAtomicType -> Cat(my_addr_byte, my_operand_size, my_opcode, alloc),
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Acquire.getPrefetchType -> Cat(M_XRD, alloc),
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Acquire.getPrefetchType -> Cat(M_XRD, alloc),
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Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
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Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
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}
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}
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