From 270011b76809e59b8e73dfc5339c8d3b0c89f7cb Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 21 Sep 2016 17:11:57 -0700 Subject: [PATCH 1/8] [unittest] more Config cleanup --- src/main/scala/unittest/Configs.scala | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index e11a4430..2615d84b 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -2,8 +2,6 @@ package unittest -import scala.collection.mutable.LinkedHashSet - import Chisel._ import cde.{Parameters, Config, CDEMatchError} import coreplex._ @@ -11,7 +9,6 @@ import rocketchip._ class WithJunctionsUnitTests extends Config( (pname, site, here) => pname match { - case RegressionTestNames => LinkedHashSet("rv64ui-p-simple") case UnitTests => (p: Parameters) => { TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) @@ -27,16 +24,17 @@ class WithUncoreUnitTests extends Config( (pname, site, here) => pname match { case NCoreplexExtClients => 0 case uncore.tilelink.TLId => "L1toL2" - case RegressionTestNames => LinkedHashSet("rv64ui-p-simple") case UnitTests => (p: Parameters) => { TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) Seq( Module(new uncore.devices.ROMSlaveTest()(p)), Module(new uncore.devices.TileLinkRAMTest()(p)), - Module(new uncore.tilelink2.TLFuzzRAMTest)) + Module(new uncore.tilelink2.TLFuzzRAMTest) + ) } case _ => throw new CDEMatchError - }) + } +) class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig) From fd5e00fed96dba3591f085b8f4c6f04b25367832 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 21 Sep 2016 17:35:39 -0700 Subject: [PATCH 2/8] [coreplex] rename Testing.scala -> RocketTestSuite.scala --- src/main/scala/coreplex/{Testing.scala => RocketTestSuite.scala} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename src/main/scala/coreplex/{Testing.scala => RocketTestSuite.scala} (100%) diff --git a/src/main/scala/coreplex/Testing.scala b/src/main/scala/coreplex/RocketTestSuite.scala similarity index 100% rename from src/main/scala/coreplex/Testing.scala rename to src/main/scala/coreplex/RocketTestSuite.scala From 64fe0103697a27cae851325b68b1e963cdd086c8 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 21 Sep 2016 17:40:39 -0700 Subject: [PATCH 3/8] [unittest] Config import tweaks --- src/main/scala/unittest/Configs.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index 2615d84b..9273b440 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -4,8 +4,8 @@ package unittest import Chisel._ import cde.{Parameters, Config, CDEMatchError} -import coreplex._ -import rocketchip._ +import coreplex.{TestGeneration, DefaultTestSuites} +import rocketchip.BaseConfig class WithJunctionsUnitTests extends Config( (pname, site, here) => pname match { @@ -22,7 +22,7 @@ class WithJunctionsUnitTests extends Config( class WithUncoreUnitTests extends Config( (pname, site, here) => pname match { - case NCoreplexExtClients => 0 + case rocketchip.NCoreplexExtClients => 0 case uncore.tilelink.TLId => "L1toL2" case UnitTests => (p: Parameters) => { TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why From 47c5d1a99299494a1ec7a5a1dd61e2615bd26d23 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 22 Sep 2016 14:31:45 -0700 Subject: [PATCH 4/8] [WIP] Move RocketTestSuite generation into RocketchipGenerator --- src/main/scala/coreplex/Configs.scala | 58 ------ src/main/scala/groundtest/Configs.scala | 3 - src/main/scala/rocketchip/BaseTop.scala | 2 +- src/main/scala/rocketchip/Generator.scala | 180 +++++++----------- .../RocketTestSuite.scala | 9 +- src/main/scala/unittest/Configs.scala | 35 ++-- src/main/scala/util/GeneratorUtils.scala | 125 ++++++++++++ 7 files changed, 214 insertions(+), 198 deletions(-) rename src/main/scala/{coreplex => rocketchip}/RocketTestSuite.scala (97%) create mode 100644 src/main/scala/util/GeneratorUtils.scala diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index f763d5b6..b2756fbc 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -13,8 +13,6 @@ import rocket._ import rocket.Util._ import util.ConfigUtils._ import rocketchip.{GlobalAddrMap, NCoreplexExtClients} -import scala.collection.mutable.{LinkedHashSet, ListBuffer} -import DefaultTestSuites._ import cde.{Parameters, Config, Dump, Knob, CDEMatchError} class BaseCoreplexConfig extends Config ( @@ -71,28 +69,6 @@ class BaseCoreplexConfig extends Config ( case NUncachedTileLinkPorts => 1 //Tile Constants case BuildTiles => { - val env = if(site(UseVM)) List("p","v") else List("p") - site(FPUKey) foreach { case cfg => - if (site(XLen) == 32) { - TestGeneration.addSuites(env.map(rv32ufNoDiv)) - } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64ufNoDiv)) - TestGeneration.addSuites(env.map(rv64udNoDiv)) - if (cfg.divSqrt) { - TestGeneration.addSuites(env.map(rv64uf)) - TestGeneration.addSuites(env.map(rv64ud)) - } - } - } - if (site(UseAtomics)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua)) - if (site(UseCompressed)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc)) - val (rvi, rvu) = - if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u) - else ((if (site(UseVM)) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) => Module(new RocketTile(resetSignal = r)(p.alterPartial({ case TileId => i @@ -187,32 +163,6 @@ class BaseCoreplexConfig extends Config ( case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64) case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case EnableL2Logging => false - case RegressionTestNames => LinkedHashSet( - "rv64ud-v-fcvt", - "rv64ud-p-fdiv", - "rv64ud-v-fadd", - "rv64uf-v-fadd", - "rv64um-v-mul", - "rv64mi-p-breakpoint", - "rv64uc-v-rvc", - "rv64ud-v-structural", - "rv64si-p-wfi", - "rv64um-v-divw", - "rv64ua-v-lrsc", - "rv64ui-v-fence_i", - "rv64ud-v-fcvt_w", - "rv64uf-v-fmin", - "rv64ui-v-sb", - "rv64ua-v-amomax_d", - "rv64ud-v-move", - "rv64ud-v-fclass", - "rv64ua-v-amoand_d", - "rv64ua-v-amoxor_d", - "rv64si-p-sbreak", - "rv64ud-v-fmadd", - "rv64uf-v-ldst", - "rv64um-v-mulh", - "rv64si-p-dirty") case _ => throw new CDEMatchError }}, knobValues = { @@ -327,14 +277,6 @@ class WithRV32 extends Config( (pname,site,here) => pname match { case XLen => 32 case FPUKey => Some(FPUConfig(divSqrt = false)) - case RegressionTestNames => LinkedHashSet( - "rv32mi-p-ma_addr", - "rv32mi-p-csr", - "rv32ui-p-sh", - "rv32ui-p-lh", - "rv32uc-p-rvc", - "rv32mi-p-sbreak", - "rv32ui-p-sll") case _ => throw new CDEMatchError } ) diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 2a450de7..d05a63d8 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -7,8 +7,6 @@ import uncore.coherence._ import uncore.agents._ import uncore.devices.NTiles import junctions._ -import scala.collection.mutable.LinkedHashSet -import scala.collection.immutable.HashMap import cde.{Parameters, Config, Dump, Knob, CDEMatchError} import scala.math.max import coreplex._ @@ -125,7 +123,6 @@ class WithGroundTest extends Config( case FPUKey => None case UseAtomics => false case UseCompressed => false - case RegressionTestNames => LinkedHashSet("rv64ui-p-simple") case _ => throw new CDEMatchError }) diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 0e18916b..de28f432 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -8,7 +8,7 @@ import junctions._ import uncore.tilelink._ import uncore.tilelink2._ import uncore.devices._ -import util.ParameterizedBundle +import util.{ParameterizedBundle, ConfigStringOutput} import rocket._ import rocket.Util._ import coreplex._ diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala index 04c47db7..f2063ecf 100644 --- a/src/main/scala/rocketchip/Generator.scala +++ b/src/main/scala/rocketchip/Generator.scala @@ -3,121 +3,79 @@ package rocketchip import Chisel._ -import scala.collection.mutable.{LinkedHashSet,LinkedHashMap} -import cde._ -import coreplex._ -import java.io.{File, FileWriter} - -/** Representation of the information this Generator needs to collect from external sources. */ -case class ParsedInputNames( - targetDir: String, - topModuleProject: String, - topModuleClass: String, - configProject: String, - configs: String) { - val configClasses: Seq[String] = configs.split('_') - val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _) - val fullTopModuleClass: String = topModuleProject + "." + topModuleClass -} - -/** Common utilities we supply to all Generators. In particular, supplies the - * canonical ways of building various JVM elaboration-time structures. - */ -trait HasGeneratorUtilities { - def getConfig(names: ParsedInputNames): Config = { - names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) => - val currentConfig = try { - Class.forName(currentName).newInstance.asInstanceOf[Config] - } catch { - case e: java.lang.ClassNotFoundException => - throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e) - } - currentConfig ++ config - } - } - - def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names)) - - def getParameters(config: Config): Parameters = Parameters.root(config.toInstance) - - import chisel3.internal.firrtl.Circuit - def elaborate(names: ParsedInputNames, params: Parameters): Circuit = { - val gen = () => - Class.forName(names.fullTopModuleClass) - .getConstructor(classOf[cde.Parameters]) - .newInstance(params) - .asInstanceOf[Module] - - Driver.elaborate(gen) - } - - def writeOutputFile(targetDir: String, fname: String, contents: String): File = { - val f = new File(targetDir, fname) - val fw = new FileWriter(f) - fw.write(contents) - fw.close - f - } -} - - -/** Standardized command line interface for Scala entry point */ -trait Generator extends App with HasGeneratorUtilities { - lazy val names: ParsedInputNames = { - require(args.size == 5, "Usage: sbt> " + - "run TargetDir TopModuleProjectName TopModuleName ConfigProjectName ConfigNameString") - ParsedInputNames( - targetDir = args(0), - topModuleProject = args(1), - topModuleClass = args(2), - configProject = args(3), - configs = args(4)) - } - - // Canonical ways of building various JVM elaboration-time structures - lazy val td = names.targetDir - lazy val config = getConfig(names) - lazy val world = config.toInstance - lazy val params = Parameters.root(world) - lazy val circuit = elaborate(names, params) - - val longName: String // Exhaustive name used to interface with external build tool targets - - /** Output FIRRTL, which an external compiler can turn into Verilog. */ - def generateFirrtl { - Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL - } - - /** Output software test Makefrags, which provide targets for integration testing. */ - def generateTestSuiteMakefrags { - TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames))) - writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites - } - - /** Output Design Space Exploration knobs and constraints. */ - def generateDSEConstraints { - writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE - writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE - } - - /** Output a global Parameter dump, which an external script can turn into Verilog headers. */ - def generateParameterDump { - writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump() - } - - /** Output a global ConfigString, for use by the RISC-V software ecosystem. */ - def generateConfigString { - ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software - } -} - -object ConfigStringOutput { - var contents: Option[String] = None -} +import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey} +import util.Generator +import scala.collection.mutable.LinkedHashSet /** An example Generator */ object RocketChipGenerator extends Generator { + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") + + override def addTestSuites { + import DefaultTestSuites._ + val xlen = params(XLen) + val vm = params(UseVM) + val env = if (vm) List("p","v") else List("p") + params(FPUKey) foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32ufNoDiv)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64ufNoDiv)) + TestGeneration.addSuites(env.map(rv64udNoDiv)) + if (cfg.divSqrt) { + TestGeneration.addSuites(env.map(rv64uf)) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + } + if (params(UseAtomics)) TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + if (params(UseCompressed)) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + val longName = names.topModuleProject + "." + names.configs generateFirrtl generateTestSuiteMakefrags diff --git a/src/main/scala/coreplex/RocketTestSuite.scala b/src/main/scala/rocketchip/RocketTestSuite.scala similarity index 97% rename from src/main/scala/coreplex/RocketTestSuite.scala rename to src/main/scala/rocketchip/RocketTestSuite.scala index 98a5a2b6..27a4522c 100644 --- a/src/main/scala/coreplex/RocketTestSuite.scala +++ b/src/main/scala/rocketchip/RocketTestSuite.scala @@ -1,12 +1,9 @@ // See LICENSE for license details. -package coreplex +package rocketchip import Chisel._ -import scala.collection.mutable.{LinkedHashSet,LinkedHashMap} -import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError} - -case object RegressionTestNames extends Field[LinkedHashSet[String]] +import scala.collection.mutable.{LinkedHashSet, LinkedHashMap} abstract class RocketTestSuite { val dir: String @@ -175,6 +172,8 @@ object DefaultTestSuites { val emptyBmarks = new BenchmarkTestSuite("empty", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty) + val singleRegression = new RegressionTestSuite(LinkedHashSet("rv64iu-p-simple")) + val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt", LinkedHashSet(((0 to 4).map("vvadd"+_) ++ List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az", diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index 9273b440..682713e6 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -4,37 +4,32 @@ package unittest import Chisel._ import cde.{Parameters, Config, CDEMatchError} -import coreplex.{TestGeneration, DefaultTestSuites} -import rocketchip.BaseConfig +import rocketchip.{BaseConfig, BasePlatformConfig} class WithJunctionsUnitTests extends Config( (pname, site, here) => pname match { - case UnitTests => (p: Parameters) => { - TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why - TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) - Seq( - Module(new junctions.MultiWidthFifoTest), - Module(new junctions.NastiMemoryDemuxTest()(p)), - Module(new junctions.HastiTest()(p))) - } + case junctions.PAddrBits => 32 + case rocket.XLen => 64 + case UnitTests => (p: Parameters) => Seq( + Module(new junctions.MultiWidthFifoTest), + Module(new junctions.NastiMemoryDemuxTest()(p)), + Module(new junctions.HastiTest()(p))) case _ => throw new CDEMatchError }) +class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new BasePlatformConfig) + class WithUncoreUnitTests extends Config( (pname, site, here) => pname match { case rocketchip.NCoreplexExtClients => 0 case uncore.tilelink.TLId => "L1toL2" - case UnitTests => (p: Parameters) => { - TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why - TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) - Seq( - Module(new uncore.devices.ROMSlaveTest()(p)), - Module(new uncore.devices.TileLinkRAMTest()(p)), - Module(new uncore.tilelink2.TLFuzzRAMTest) - ) - } + case UnitTests => (p: Parameters) => Seq( + Module(new uncore.devices.ROMSlaveTest()(p)), + Module(new uncore.devices.TileLinkRAMTest()(p)), + Module(new uncore.tilelink2.TLFuzzRAMTest)) case _ => throw new CDEMatchError } ) -class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig) +class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseConfig) + diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala new file mode 100644 index 00000000..3b91b578 --- /dev/null +++ b/src/main/scala/util/GeneratorUtils.scala @@ -0,0 +1,125 @@ +// See LICENSE for license details. + +package util + +import Chisel._ +import cde._ +import java.io.{File, FileWriter} + +/** Representation of the information this Generator needs to collect from external sources. */ +case class ParsedInputNames( + targetDir: String, + topModuleProject: String, + topModuleClass: String, + configProject: String, + configs: String) { + val configClasses: Seq[String] = configs.split('_') + val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _) + val fullTopModuleClass: String = topModuleProject + "." + topModuleClass +} + +/** Common utilities we supply to all Generators. In particular, supplies the + * canonical ways of building various JVM elaboration-time structures. + */ +trait HasGeneratorUtilities { + def getConfig(names: ParsedInputNames): Config = { + names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) => + val currentConfig = try { + Class.forName(currentName).newInstance.asInstanceOf[Config] + } catch { + case e: java.lang.ClassNotFoundException => + throwException(s"""Unable to find part "$currentName" from "${names.configs}", did you misspell it?""", e) + } + currentConfig ++ config + } + } + + def getParameters(names: ParsedInputNames): Parameters = getParameters(getConfig(names)) + + def getParameters(config: Config): Parameters = Parameters.root(config.toInstance) + + import chisel3.internal.firrtl.Circuit + def elaborate(names: ParsedInputNames, params: Parameters): Circuit = { + val gen = () => + Class.forName(names.fullTopModuleClass) + .getConstructor(classOf[cde.Parameters]) + .newInstance(params) + .asInstanceOf[Module] + + Driver.elaborate(gen) + } + + def writeOutputFile(targetDir: String, fname: String, contents: String): File = { + val f = new File(targetDir, fname) + val fw = new FileWriter(f) + fw.write(contents) + fw.close + f + } +} + + +/** Standardized command line interface for Scala entry point */ +trait Generator extends App with HasGeneratorUtilities { + lazy val names: ParsedInputNames = { + require(args.size == 5, "Usage: sbt> " + + "run TargetDir TopModuleProjectName TopModuleName " + + "ConfigProjectName ConfigNameString") + ParsedInputNames( + targetDir = args(0), + topModuleProject = args(1), + topModuleClass = args(2), + configProject = args(3), + configs = args(4)) + } + + // Canonical ways of building various JVM elaboration-time structures + lazy val td = names.targetDir + lazy val config = getConfig(names) + lazy val world = config.toInstance + lazy val params = Parameters.root(world) + lazy val circuit = elaborate(names, params) + + val longName: String // Exhaustive name used to interface with external build tool targets + + /** Output FIRRTL, which an external compiler can turn into Verilog. */ + def generateFirrtl { + Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL + } + + /** Output software test Makefrags, which provide targets for integration testing. */ + def generateTestSuiteMakefrags { + addTestSuites + writeOutputFile(td, s"$longName.d", rocketchip.TestGeneration.generateMakefrag) // Coreplex-specific test suites + } + + def addTestSuites { + // TODO: better job of Makefrag generation + // for non-RocketChip testing platforms + import rocketchip.{DefaultTestSuites, TestGeneration} + TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) + TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) + TestGeneration.addSuite(DefaultTestSuites.singleRegression) + } + + /** Output Design Space Exploration knobs and constraints. */ + def generateDSEConstraints { + writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE + writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE + } + + /** Output a global Parameter dump, which an external script can turn into Verilog headers. */ + def generateParameterDump { + writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump() + } + + /** Output a global ConfigString, for use by the RISC-V software ecosystem. */ + def generateConfigString { + ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) + } +} + +object ConfigStringOutput { + var contents: Option[String] = None +} + From 83c08a931d044b0ed9a37041d76c47b58dabe6ab Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 22 Sep 2016 14:57:18 -0700 Subject: [PATCH 5/8] [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator --- regression/Makefile | 2 +- src/main/scala/groundtest/Configs.scala | 16 +- src/main/scala/groundtest/Generator.scala | 217 +----------------- src/main/scala/groundtest/NastiTest.scala | 2 +- .../scala/groundtest/TrafficGenerator.scala | 213 +++++++++++++++++ src/main/scala/rocketchip/Generator.scala | 2 +- src/main/scala/unittest/Generator.scala | 14 ++ 7 files changed, 244 insertions(+), 222 deletions(-) create mode 100644 src/main/scala/groundtest/TrafficGenerator.scala create mode 100644 src/main/scala/unittest/Generator.scala diff --git a/regression/Makefile b/regression/Makefile index 95a23319..741ad356 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -52,7 +52,7 @@ endif ifeq ($(SUITE),UnittestSuite) PROJECT=unittest -CONFIGS=UnitTestConfig +CONFIGS=JunctionsUnitTestConfig, UncoreUnitTestConfig endif ifeq ($(SUITE), JtagDtmSuite) diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index d05a63d8..d57a8fa5 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -100,12 +100,6 @@ class WithGroundTest extends Config( dataBits = site(CacheBlockBytes)*8) } case BuildTiles => { - val groundtest = if (site(XLen) == 64) - DefaultTestSuites.groundtest64 - else - DefaultTestSuites.groundtest32 - TestGeneration.addSuite(groundtest("p")) - TestGeneration.addSuite(DefaultTestSuites.emptyBmarks) (0 until site(NTiles)).map { i => val tileSettings = site(GroundTestKey)(i) (r: Bool, p: Parameters) => { @@ -163,7 +157,7 @@ class WithMemtest extends Config( case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(1, 1) } - case GeneratorKey => GeneratorParameters( + case GeneratorKey => TrafficGeneratorParameters( maxRequests = 128, startAddress = site(GlobalAddrMap)("mem").start) case BuildGroundTest => @@ -223,7 +217,7 @@ class WithNastiConverterTest extends Config( case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 1) } - case GeneratorKey => GeneratorParameters( + case GeneratorKey => TrafficGeneratorParameters( maxRequests = 128, startAddress = site(GlobalAddrMap)("mem").start) case BuildGroundTest => @@ -238,7 +232,7 @@ class WithTraceGen extends Config( } case BuildGroundTest => (p: Parameters) => Module(new GroundTestTraceGenerator()(p)) - case GeneratorKey => GeneratorParameters( + case GeneratorKey => TrafficGeneratorParameters( maxRequests = 256, startAddress = 0) case AddressBag => { @@ -266,7 +260,7 @@ class WithPCIeMockupTest extends Config( case GroundTestKey => Seq( GroundTestTileSettings(1, 1), GroundTestTileSettings(1)) - case GeneratorKey => GeneratorParameters( + case GeneratorKey => TrafficGeneratorParameters( maxRequests = 128, startAddress = site(GlobalAddrMap)("mem").start) case BuildGroundTest => @@ -282,7 +276,7 @@ class WithDirectMemtest extends Config( val nGens = 8 pname match { case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens)) - case GeneratorKey => GeneratorParameters( + case GeneratorKey => TrafficGeneratorParameters( maxRequests = 1024, startAddress = 0) case BuildGroundTest => diff --git a/src/main/scala/groundtest/Generator.scala b/src/main/scala/groundtest/Generator.scala index 221bb7eb..72b55108 100644 --- a/src/main/scala/groundtest/Generator.scala +++ b/src/main/scala/groundtest/Generator.scala @@ -1,213 +1,14 @@ +// See LICENSE for license details. + package groundtest import Chisel._ -import uncore.tilelink._ -import uncore.devices.NTiles -import uncore.constants._ -import junctions._ -import rocket._ -import util.SimpleTimer -import scala.util.Random -import cde.{Parameters, Field} +import util.Generator -case class GeneratorParameters( - maxRequests: Int, - startAddress: BigInt) -case object GeneratorKey extends Field[GeneratorParameters] - -trait HasGeneratorParameters extends HasGroundTestParameters { - implicit val p: Parameters - - val genParams = p(GeneratorKey) - val nGens = p(GroundTestKey).map( - cs => cs.uncached + cs.cached).reduce(_ + _) - val genTimeout = 8192 - val maxRequests = genParams.maxRequests - val startAddress = genParams.startAddress - - val genWordBits = 32 - val genWordBytes = genWordBits / 8 - val wordOffset = log2Ceil(genWordBytes) - val wordSize = UInt(log2Ceil(genWordBytes)) - - require(startAddress % BigInt(genWordBytes) == 0) -} - -class UncachedTileLinkGenerator(id: Int) - (implicit p: Parameters) extends TLModule()(p) with HasGeneratorParameters { - - private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits - - val io = new Bundle { - val mem = new ClientUncachedTileLinkIO - val status = new GroundTestStatus - } - - val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4) - val state = Reg(init = s_start) - - val (req_cnt, req_wrap) = Counter(io.mem.grant.fire(), maxRequests) - - val sending = Reg(init = Bool(false)) - - when (state === s_start) { - sending := Bool(true) - state := s_put - } - - when (io.mem.acquire.fire()) { sending := Bool(false) } - when (io.mem.grant.fire()) { sending := Bool(true) } - when (req_wrap) { state := Mux(state === s_put, s_get, s_finished) } - - val timeout = SimpleTimer(genTimeout, io.mem.acquire.fire(), io.mem.grant.fire()) - assert(!timeout, s"Uncached generator ${id} timed out waiting for grant") - - io.status.finished := (state === s_finished) - io.status.timeout.valid := timeout - io.status.timeout.bits := UInt(id) - - val part_of_full_addr = - if (log2Ceil(nGens) > 0) { - Cat(UInt(id, log2Ceil(nGens)), - UInt(0, wordOffset)) - } else { - UInt(0, wordOffset) - } - val full_addr = UInt(startAddress) + Cat(req_cnt, part_of_full_addr) - - val addr_block = full_addr >> UInt(tlBlockOffset) - val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits) - val addr_byte = full_addr(tlByteAddrBits - 1, 0) - - val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt) - val word_data = Wire(UInt(width = genWordBits)) - word_data := Cat(data_prefix, part_of_full_addr) - val beat_data = Fill(tlDataBits / genWordBits, word_data) - val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset)) - val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift - - val put_acquire = Put( - client_xact_id = UInt(0), - addr_block = addr_block, - addr_beat = addr_beat, - data = beat_data, - wmask = Some(wmask), - alloc = Bool(false)) - - val get_acquire = Get( - client_xact_id = UInt(0), - addr_block = addr_block, - addr_beat = addr_beat, - addr_byte = addr_byte, - operand_size = wordSize, - alloc = Bool(false)) - - io.mem.acquire.valid := sending && !io.status.finished - io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire) - io.mem.grant.ready := !sending && !io.status.finished - - def wordFromBeat(addr: UInt, dat: UInt) = { - val shift = Cat(beatOffset(addr), UInt(0, wordOffset + 3)) - (dat >> shift)(genWordBits - 1, 0) - } - - val data_mismatch = io.mem.grant.fire() && state === s_get && - wordFromBeat(full_addr, io.mem.grant.bits.data) =/= word_data - - io.status.error.valid := data_mismatch - io.status.error.bits := UInt(id) - - assert(!data_mismatch, - s"Get received incorrect data in uncached generator ${id}") - - def beatOffset(addr: UInt) = // TODO zero-width - if (tlByteAddrBits > wordOffset) addr(tlByteAddrBits - 1, wordOffset) - else UInt(0) -} - -class HellaCacheGenerator(id: Int) - (implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParameters { - val io = new Bundle { - val mem = new HellaCacheIO - val status = new GroundTestStatus - } - - val timeout = SimpleTimer(genTimeout, io.mem.req.fire(), io.mem.resp.valid) - assert(!timeout, s"Cached generator ${id} timed out waiting for response") - io.status.timeout.valid := timeout - io.status.timeout.bits := UInt(id) - - val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4) - val state = Reg(init = s_start) - val sending = Reg(init = Bool(false)) - - val (req_cnt, req_wrap) = Counter(io.mem.resp.valid, maxRequests) - - val part_of_req_addr = - if (log2Ceil(nGens) > 0) { - Cat(UInt(id, log2Ceil(nGens)), - UInt(0, wordOffset)) - } else { - UInt(0, wordOffset) - } - val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr) - val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, part_of_req_addr) - - io.mem.req.valid := sending && !io.status.finished - io.mem.req.bits.addr := req_addr - io.mem.req.bits.data := req_data - io.mem.req.bits.typ := wordSize - io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) - io.mem.req.bits.tag := UInt(0) - - when (state === s_start) { sending := Bool(true); state := s_write } - - when (io.mem.req.fire()) { sending := Bool(false) } - when (io.mem.resp.valid) { sending := Bool(true) } - - when (req_wrap) { state := Mux(state === s_write, s_read, s_finished) } - - io.status.finished := (state === s_finished) - - def data_match(recv: Bits, expected: Bits): Bool = { - val recv_resized = Wire(Bits(width = genWordBits)) - val exp_resized = Wire(Bits(width = genWordBits)) - - recv_resized := recv - exp_resized := expected - recv_resized === exp_resized - } - - val data_mismatch = io.mem.resp.valid && io.mem.resp.bits.has_data && - !data_match(io.mem.resp.bits.data, req_data) - - io.status.error.valid := data_mismatch - io.status.error.bits := UInt(id) - - assert(!data_mismatch, - s"Received incorrect data in cached generator ${id}") -} - -class GeneratorTest(implicit p: Parameters) - extends GroundTest()(p) with HasGeneratorParameters { - - val idStart = p(GroundTestKey).take(p(TileId)) - .map(settings => settings.cached + settings.uncached) - .foldLeft(0)(_ + _) - - val cached = List.tabulate(nCached) { i => - val realId = idStart + i - Module(new HellaCacheGenerator(realId)) - } - - val uncached = List.tabulate(nUncached) { i => - val realId = idStart + nCached + i - Module(new UncachedTileLinkGenerator(realId)) - } - - io.cache <> cached.map(_.io.mem) - io.mem <> uncached.map(_.io.mem) - - val gen_debug = cached.map(_.io.status) ++ uncached.map(_.io.status) - io.status := DebugCombiner(gen_debug) +object GroundtestGenerator extends Generator +{ + val longName = names.topModuleProject + "." + names.configs + generateFirrtl + generateTestSuiteMakefrags // TODO: Needed only for legacy make targets + generateParameterDump // TODO: Needed only for legacy make targets } diff --git a/src/main/scala/groundtest/NastiTest.scala b/src/main/scala/groundtest/NastiTest.scala index 4b419834..1832a831 100644 --- a/src/main/scala/groundtest/NastiTest.scala +++ b/src/main/scala/groundtest/NastiTest.scala @@ -12,7 +12,7 @@ class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module with HasNastiParameters with HasMIFParameters with HasAddrMapParameters - with HasGeneratorParameters { + with HasTrafficGeneratorParameters { val io = new Bundle { val status = new GroundTestStatus diff --git a/src/main/scala/groundtest/TrafficGenerator.scala b/src/main/scala/groundtest/TrafficGenerator.scala new file mode 100644 index 00000000..af2aeb50 --- /dev/null +++ b/src/main/scala/groundtest/TrafficGenerator.scala @@ -0,0 +1,213 @@ +package groundtest + +import Chisel._ +import uncore.tilelink._ +import uncore.devices.NTiles +import uncore.constants._ +import junctions._ +import rocket._ +import util.SimpleTimer +import scala.util.Random +import cde.{Parameters, Field} + +case class TrafficGeneratorParameters( + maxRequests: Int, + startAddress: BigInt) +case object GeneratorKey extends Field[TrafficGeneratorParameters] + +trait HasTrafficGeneratorParameters extends HasGroundTestParameters { + implicit val p: Parameters + + val genParams = p(GeneratorKey) + val nGens = p(GroundTestKey).map( + cs => cs.uncached + cs.cached).reduce(_ + _) + val genTimeout = 8192 + val maxRequests = genParams.maxRequests + val startAddress = genParams.startAddress + + val genWordBits = 32 + val genWordBytes = genWordBits / 8 + val wordOffset = log2Ceil(genWordBytes) + val wordSize = UInt(log2Ceil(genWordBytes)) + + require(startAddress % BigInt(genWordBytes) == 0) +} + +class UncachedTileLinkGenerator(id: Int) + (implicit p: Parameters) extends TLModule()(p) with HasTrafficGeneratorParameters { + + private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits + + val io = new Bundle { + val mem = new ClientUncachedTileLinkIO + val status = new GroundTestStatus + } + + val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4) + val state = Reg(init = s_start) + + val (req_cnt, req_wrap) = Counter(io.mem.grant.fire(), maxRequests) + + val sending = Reg(init = Bool(false)) + + when (state === s_start) { + sending := Bool(true) + state := s_put + } + + when (io.mem.acquire.fire()) { sending := Bool(false) } + when (io.mem.grant.fire()) { sending := Bool(true) } + when (req_wrap) { state := Mux(state === s_put, s_get, s_finished) } + + val timeout = SimpleTimer(genTimeout, io.mem.acquire.fire(), io.mem.grant.fire()) + assert(!timeout, s"Uncached generator ${id} timed out waiting for grant") + + io.status.finished := (state === s_finished) + io.status.timeout.valid := timeout + io.status.timeout.bits := UInt(id) + + val part_of_full_addr = + if (log2Ceil(nGens) > 0) { + Cat(UInt(id, log2Ceil(nGens)), + UInt(0, wordOffset)) + } else { + UInt(0, wordOffset) + } + val full_addr = UInt(startAddress) + Cat(req_cnt, part_of_full_addr) + + val addr_block = full_addr >> UInt(tlBlockOffset) + val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits) + val addr_byte = full_addr(tlByteAddrBits - 1, 0) + + val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt) + val word_data = Wire(UInt(width = genWordBits)) + word_data := Cat(data_prefix, part_of_full_addr) + val beat_data = Fill(tlDataBits / genWordBits, word_data) + val wshift = Cat(beatOffset(full_addr), UInt(0, wordOffset)) + val wmask = Fill(genWordBits / 8, Bits(1, 1)) << wshift + + val put_acquire = Put( + client_xact_id = UInt(0), + addr_block = addr_block, + addr_beat = addr_beat, + data = beat_data, + wmask = Some(wmask), + alloc = Bool(false)) + + val get_acquire = Get( + client_xact_id = UInt(0), + addr_block = addr_block, + addr_beat = addr_beat, + addr_byte = addr_byte, + operand_size = wordSize, + alloc = Bool(false)) + + io.mem.acquire.valid := sending && !io.status.finished + io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire) + io.mem.grant.ready := !sending && !io.status.finished + + def wordFromBeat(addr: UInt, dat: UInt) = { + val shift = Cat(beatOffset(addr), UInt(0, wordOffset + 3)) + (dat >> shift)(genWordBits - 1, 0) + } + + val data_mismatch = io.mem.grant.fire() && state === s_get && + wordFromBeat(full_addr, io.mem.grant.bits.data) =/= word_data + + io.status.error.valid := data_mismatch + io.status.error.bits := UInt(id) + + assert(!data_mismatch, + s"Get received incorrect data in uncached generator ${id}") + + def beatOffset(addr: UInt) = // TODO zero-width + if (tlByteAddrBits > wordOffset) addr(tlByteAddrBits - 1, wordOffset) + else UInt(0) +} + +class HellaCacheGenerator(id: Int) + (implicit p: Parameters) extends L1HellaCacheModule()(p) with HasTrafficGeneratorParameters { + val io = new Bundle { + val mem = new HellaCacheIO + val status = new GroundTestStatus + } + + val timeout = SimpleTimer(genTimeout, io.mem.req.fire(), io.mem.resp.valid) + assert(!timeout, s"Cached generator ${id} timed out waiting for response") + io.status.timeout.valid := timeout + io.status.timeout.bits := UInt(id) + + val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4) + val state = Reg(init = s_start) + val sending = Reg(init = Bool(false)) + + val (req_cnt, req_wrap) = Counter(io.mem.resp.valid, maxRequests) + + val part_of_req_addr = + if (log2Ceil(nGens) > 0) { + Cat(UInt(id, log2Ceil(nGens)), + UInt(0, wordOffset)) + } else { + UInt(0, wordOffset) + } + val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr) + val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, part_of_req_addr) + + io.mem.req.valid := sending && !io.status.finished + io.mem.req.bits.addr := req_addr + io.mem.req.bits.data := req_data + io.mem.req.bits.typ := wordSize + io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) + io.mem.req.bits.tag := UInt(0) + + when (state === s_start) { sending := Bool(true); state := s_write } + + when (io.mem.req.fire()) { sending := Bool(false) } + when (io.mem.resp.valid) { sending := Bool(true) } + + when (req_wrap) { state := Mux(state === s_write, s_read, s_finished) } + + io.status.finished := (state === s_finished) + + def data_match(recv: Bits, expected: Bits): Bool = { + val recv_resized = Wire(Bits(width = genWordBits)) + val exp_resized = Wire(Bits(width = genWordBits)) + + recv_resized := recv + exp_resized := expected + recv_resized === exp_resized + } + + val data_mismatch = io.mem.resp.valid && io.mem.resp.bits.has_data && + !data_match(io.mem.resp.bits.data, req_data) + + io.status.error.valid := data_mismatch + io.status.error.bits := UInt(id) + + assert(!data_mismatch, + s"Received incorrect data in cached generator ${id}") +} + +class GeneratorTest(implicit p: Parameters) + extends GroundTest()(p) with HasTrafficGeneratorParameters { + + val idStart = p(GroundTestKey).take(p(TileId)) + .map(settings => settings.cached + settings.uncached) + .foldLeft(0)(_ + _) + + val cached = List.tabulate(nCached) { i => + val realId = idStart + i + Module(new HellaCacheGenerator(realId)) + } + + val uncached = List.tabulate(nUncached) { i => + val realId = idStart + nCached + i + Module(new UncachedTileLinkGenerator(realId)) + } + + io.cache <> cached.map(_.io.mem) + io.mem <> uncached.map(_.io.mem) + + val gen_debug = cached.map(_.io.status) ++ uncached.map(_.io.status) + io.status := DebugCombiner(gen_debug) +} diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala index f2063ecf..fd9aa81d 100644 --- a/src/main/scala/rocketchip/Generator.scala +++ b/src/main/scala/rocketchip/Generator.scala @@ -7,7 +7,7 @@ import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey} import util.Generator import scala.collection.mutable.LinkedHashSet -/** An example Generator */ +/** A Generator for platforms containing Rocket Coreplexes */ object RocketChipGenerator extends Generator { val rv64RegrTestNames = LinkedHashSet( diff --git a/src/main/scala/unittest/Generator.scala b/src/main/scala/unittest/Generator.scala new file mode 100644 index 00000000..e50976d5 --- /dev/null +++ b/src/main/scala/unittest/Generator.scala @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +package unittest + +import Chisel._ +import util.Generator + +object UnitTestGenerator extends Generator +{ + val longName = names.topModuleProject + "." + names.configs + generateFirrtl + generateTestSuiteMakefrags // TODO: Needed only for legacy make targets + generateParameterDump // TODO: Needed only for legacy make targets +} From 411ee378def3c893de28fe103dcf38277dd2d958 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 22 Sep 2016 15:59:29 -0700 Subject: [PATCH 6/8] Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. --- Makefrag | 2 -- emulator/Makefile | 5 +---- emulator/Makefrag-verilator | 4 ++-- project/build.scala | 2 +- src/main/scala/groundtest/Generator.scala | 6 +----- src/main/scala/rocketchip/Generator.scala | 6 ++---- src/main/scala/unittest/Generator.scala | 6 +----- src/main/scala/util/GeneratorUtils.scala | 2 +- vsim/Makefrag-verilog | 2 +- 9 files changed, 10 insertions(+), 25 deletions(-) diff --git a/Makefrag b/Makefrag index e76bb737..39e01809 100644 --- a/Makefrag +++ b/Makefrag @@ -23,8 +23,6 @@ $(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala") $(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala touch $(FIRRTL_JAR) -CHISEL_ARGS := --targetDir $(generated_dir) - src_path = src/main/scala default_submodules = . hardfloat context-dependent-environments chisel3 chisel_srcs = $(foreach submodule,$(default_submodules) $(ROCKETCHIP_ADDONS),$(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala")) diff --git a/emulator/Makefile b/emulator/Makefile index 32ee7b60..9760f2d6 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -23,10 +23,7 @@ debug: $(emu_debug) clean: rm -rf *.o *.a emulator-* $(generated_dir) $(generated_dir_debug) DVEfiles $(output_dir) -test: - cd $(base_dir) && $(SBT) "~make $(CURDIR) run-fast $(CHISEL_ARGS)" - -.PHONY: default all debug clean test +.PHONY: default all debug clean #-------------------------------------------------------------------- # Run assembly tests and benchmarks diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index 1767f15b..f9e6856e 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -10,11 +10,11 @@ verilog_debug = $(generated_dir_debug)/$(long_name).v $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" $(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" %.v: %.fir $(FIRRTL_JAR) mkdir -p $(dir $@) diff --git a/project/build.scala b/project/build.scala index c8944562..80047920 100644 --- a/project/build.scala +++ b/project/build.scala @@ -32,7 +32,7 @@ object BuildSettings extends Build { a.split(" ") }, unmanagedSourceDirectories in Compile ++= addons.value.map(baseDirectory.value / _ / "src/main/scala"), - mainClass in (Compile, run) := Some("rocketchip.RocketChipGenerator"), + mainClass in (Compile, run) := Some("rocketchip.Generator"), make := { val jobs = java.lang.Runtime.getRuntime.availableProcessors val (makeDir, target) = setMake.parsed diff --git a/src/main/scala/groundtest/Generator.scala b/src/main/scala/groundtest/Generator.scala index 72b55108..f5c6bb27 100644 --- a/src/main/scala/groundtest/Generator.scala +++ b/src/main/scala/groundtest/Generator.scala @@ -2,11 +2,7 @@ package groundtest -import Chisel._ -import util.Generator - -object GroundtestGenerator extends Generator -{ +object Generator extends util.GeneratorApp { val longName = names.topModuleProject + "." + names.configs generateFirrtl generateTestSuiteMakefrags // TODO: Needed only for legacy make targets diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala index fd9aa81d..ea7d212e 100644 --- a/src/main/scala/rocketchip/Generator.scala +++ b/src/main/scala/rocketchip/Generator.scala @@ -2,14 +2,12 @@ package rocketchip -import Chisel._ import rocket.{XLen, UseVM, UseAtomics, UseCompressed, FPUKey} -import util.Generator import scala.collection.mutable.LinkedHashSet /** A Generator for platforms containing Rocket Coreplexes */ -object RocketChipGenerator extends Generator -{ +object Generator extends util.GeneratorApp { + val rv64RegrTestNames = LinkedHashSet( "rv64ud-v-fcvt", "rv64ud-p-fdiv", diff --git a/src/main/scala/unittest/Generator.scala b/src/main/scala/unittest/Generator.scala index e50976d5..95e114d1 100644 --- a/src/main/scala/unittest/Generator.scala +++ b/src/main/scala/unittest/Generator.scala @@ -2,11 +2,7 @@ package unittest -import Chisel._ -import util.Generator - -object UnitTestGenerator extends Generator -{ +object Generator extends util.GeneratorApp { val longName = names.topModuleProject + "." + names.configs generateFirrtl generateTestSuiteMakefrags // TODO: Needed only for legacy make targets diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala index 3b91b578..8937e9e4 100644 --- a/src/main/scala/util/GeneratorUtils.scala +++ b/src/main/scala/util/GeneratorUtils.scala @@ -60,7 +60,7 @@ trait HasGeneratorUtilities { /** Standardized command line interface for Scala entry point */ -trait Generator extends App with HasGeneratorUtilities { +trait GeneratorApp extends App with HasGeneratorUtilities { lazy val names: ParsedInputNames = { require(args.size == 5, "Usage: sbt> " + "run TargetDir TopModuleProjectName TopModuleName " + diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 12fb7678..0f078a21 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img) mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" + cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR) mkdir -p $(dir $@) From 91aab2fabc8ae0cb2a68c7bd50b001d8331f4c29 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 22 Sep 2016 17:28:34 -0700 Subject: [PATCH 7/8] no commas in yml --- regression/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/regression/Makefile b/regression/Makefile index 741ad356..b960cb7a 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -52,7 +52,7 @@ endif ifeq ($(SUITE),UnittestSuite) PROJECT=unittest -CONFIGS=JunctionsUnitTestConfig, UncoreUnitTestConfig +CONFIGS=JunctionsUnitTestConfig UncoreUnitTestConfig endif ifeq ($(SUITE), JtagDtmSuite) From 22053289efe7906575705e371fb7bc0b8b87b982 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 22 Sep 2016 17:33:35 -0700 Subject: [PATCH 8/8] fix typo rv64iu -> rv64ui --- src/main/scala/rocketchip/RocketTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocketchip/RocketTestSuite.scala b/src/main/scala/rocketchip/RocketTestSuite.scala index 27a4522c..cf8cfec4 100644 --- a/src/main/scala/rocketchip/RocketTestSuite.scala +++ b/src/main/scala/rocketchip/RocketTestSuite.scala @@ -172,7 +172,7 @@ object DefaultTestSuites { val emptyBmarks = new BenchmarkTestSuite("empty", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet.empty) - val singleRegression = new RegressionTestSuite(LinkedHashSet("rv64iu-p-simple")) + val singleRegression = new RegressionTestSuite(LinkedHashSet("rv64ui-p-simple")) val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt", LinkedHashSet(((0 to 4).map("vvadd"+_) ++