riscv/rocket-chip
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dcache/dtlb overhaul

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This commit is contained in:
Rimas Avizienis
2011-11-11 18:18:47 -08:00
parent e4fa94aa27
commit a1ce908541
5 changed files with 242 additions and 173 deletions
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3
rocket/src/main/scala/ctrl.scala
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@ -326,7 +326,8 @@ class rocketCtrl extends Component
val jr_taken = (ex_reg_br_type === BR_JR);
val j_taken = (ex_reg_br_type === BR_J);
io.dmem.req_val := ex_reg_mem_val; // && ~io.dpath.killx;
// io.dmem.req_val := ex_reg_mem_val;
io.dmem.req_val := ex_reg_mem_val && ~io.dpath.killx;
io.dmem.req_cmd := ex_reg_mem_cmd;
io.dmem.req_type := ex_reg_mem_type;