riscv/rocket-chip
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dcache/dtlb overhaul

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This commit is contained in:
Rimas Avizienis
2011-11-11 18:18:47 -08:00
parent e4fa94aa27
commit a1ce908541
5 changed files with 242 additions and 173 deletions
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9
rocket/src/main/scala/cpu.scala
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@ -76,7 +76,7 @@ class rocketProc extends Component
dtlb.io.cpu.req_val := ctrl.io.dmem.req_val;
dtlb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
dtlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
dtlb.io.cpu.req_addr := dpath.io.dmem.req_addr;
dtlb.io.cpu.req_vpn := dpath.io.dmem.req_addr(VADDR_BITS-1,PGIDX_BITS);
ctrl.io.xcpt_dtlb_ld := dtlb.io.cpu.xcpt_ld;
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st;
ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss;
@ -90,10 +90,13 @@ class rocketProc extends Component
arb.io.mem ^^ io.dmem
// connect arbiter to ctrl+dpath+DTLB
arb.io.cpu.req_val := dtlb.io.cpu.resp_val;
// arb.io.cpu.req_val := dtlb.io.cpu.resp_val;
arb.io.cpu.req_val := ctrl.io.dmem.req_val;
arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
arb.io.cpu.req_type := ctrl.io.dmem.req_type;
arb.io.cpu.req_addr := dtlb.io.cpu.resp_addr;
// arb.io.cpu.req_addr := dtlb.io.cpu.resp_addr;
arb.io.cpu.req_idx := dpath.io.dmem.req_addr(PGIDX_BITS-1,0);
arb.io.cpu.req_ppn := dtlb.io.cpu.resp_ppn;
arb.io.cpu.req_data := dpath.io.dmem.req_data;
arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.req_rdy := dtlb.io.cpu.req_rdy && arb.io.cpu.req_rdy;