From a1b30282ddd8eb74b1c5ff301bc9419814e0a1ae Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 9 Mar 2012 01:09:22 -0800 Subject: [PATCH] major refactoring on vector exception interface --- rocket/src/main/scala/consts.scala | 5 +++-- rocket/src/main/scala/cpu.scala | 15 +++++++-------- rocket/src/main/scala/ctrl_vec.scala | 13 +++++-------- rocket/src/main/scala/dpath.scala | 6 ++++-- rocket/src/main/scala/dpath_util.scala | 13 +++++-------- rocket/src/main/scala/dpath_vec.scala | 16 ++++++++-------- 6 files changed, 32 insertions(+), 36 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index dbc5f7c7..a3b1e4ea 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -144,8 +144,9 @@ object Constants val PCR_VECBANK = UFix(18, 5); // temporaries for vector, these will go away - val PCR_VEC_EADDR = UFix(30, 5) - val PCR_VEC_XCPT = UFix(31, 5) + val PCR_VEC_BACKUP = UFix(29, 5) + val PCR_VEC_KILL = UFix(30, 5) + val PCR_VEC_HOLD = UFix(31, 5) // definition of bits in PCR status reg val SR_ET = 0; // enable traps diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index c9ed016d..068d2de6 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -197,14 +197,13 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) ctrl.io.vec_iface.vfence_ready := vu.io.vec_fence_ready // exceptions - vu.io.xcpt_backup.exception := dpath.io.vec_iface.exception - vu.io.xcpt_backup.exception_addr := dpath.io.vec_iface.eaddr.toUFix - ctrl.io.vec_iface.exception_ack_valid := vu.io.xcpt_backup.exception_ack_valid - vu.io.xcpt_backup.exception_ack_ready := ctrl.io.vec_iface.exception_ack_ready - vu.io.xcpt_resume.hold := dpath.io.vec_iface.hold - vu.io.xcpt_kill.kill := dpath.io.vec_iface.kill - ctrl.io.vec_iface.kill_ack_valid := vu.io.xcpt_kill.kill_ack_valid - vu.io.xcpt_kill.kill_ack_ready := ctrl.io.vec_iface.kill_ack_ready + vu.io.xcpt.exception := ctrl.io.vec_iface.exception + ctrl.io.vec_iface.exception_ack_valid := vu.io.xcpt.exception_ack_valid + vu.io.xcpt.exception_ack_ready := ctrl.io.vec_iface.exception_ack_ready + vu.io.xcpt.backup := dpath.io.vec_iface.backup + vu.io.xcpt.backup_addr := dpath.io.vec_iface.backup_addr.toUFix + vu.io.xcpt.kill := dpath.io.vec_iface.kill + vu.io.xcpt.hold := dpath.io.vec_iface.hold // hooking up vector memory interface val storegen = new StoreDataGen diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 5a7deedb..2423e426 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -39,11 +39,9 @@ class ioCtrlVecInterface extends Bundle val vfence_ready = Bool(INPUT) + val exception = Bool(OUTPUT) val exception_ack_valid = Bool(INPUT) val exception_ack_ready = Bool(OUTPUT) - - val kill_ack_valid = Bool(INPUT) - val kill_ack_ready = Bool(OUTPUT) } class ioCtrlVec extends Bundle @@ -186,9 +184,6 @@ class rocketCtrlVec extends Component mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && wb_vec_pfcntq_enq - io.iface.exception_ack_ready := Bool(true) - io.iface.kill_ack_ready := Bool(true) - io.replay := valid_common && ( wb_vec_cmdq_enq && !io.iface.vcmdq_ready || wb_vec_ximm1q_enq && !io.iface.vximm1q_ready || @@ -206,8 +201,10 @@ class rocketCtrlVec extends Component when (do_waitxcpt) { reg_waitxcpt := Bool(true) } when (io.iface.exception_ack_valid) { reg_waitxcpt := Bool(false) } - when (io.iface.kill_ack_valid) { reg_waitxcpt := Bool(false) } + + io.iface.exception := io.exception && io.sr_ev + io.iface.exception_ack_ready := reg_waitxcpt io.stalld := reg_waitxcpt - io.vfence_ready := io.iface.vfence_ready + io.vfence_ready := !io.sr_ev || io.iface.vfence_ready } diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index f14f80cb..1486c3d4 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -383,8 +383,10 @@ class rocketDpath extends Component vec.io.vecbankcnt := pcr.io.vecbankcnt vec.io.wdata := wb_reg_vec_wdata vec.io.rs2 := wb_reg_rs2 - vec.io.vec_eaddr := pcr.io.vec_eaddr - vec.io.vec_xcpt := pcr.io.vec_xcpt + vec.io.vechold := pcr.io.vechold + vec.io.pcrw.addr := wb_reg_raddr2 + vec.io.pcrw.en := io.ctrl.wen_pcr + vec.io.pcrw.data := wb_reg_wdata wb_wdata := Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl), diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 7353c91f..2748048c 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -79,8 +79,7 @@ class ioDpathPCR extends Bundle() val irq_ipi = Bool(OUTPUT); val vecbank = Bits(8, OUTPUT) val vecbankcnt = UFix(4, OUTPUT) - val vec_eaddr = Bits(VADDR_BITS, OUTPUT) - val vec_xcpt = Bits(3, OUTPUT) + val vechold = Bool(OUTPUT) } class rocketDpathPCR extends Component @@ -99,8 +98,7 @@ class rocketDpathPCR extends Component val reg_k1 = Reg() { Bits() }; val reg_ptbr = Reg() { UFix() }; val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8)) - val reg_vec_eaddr = Reg() { Bits() } - val reg_vec_xcpt = Reg() { Bits() } + val reg_vechold = Reg() { Bool() } val reg_error_mode = Reg(resetVal = Bool(false)); val reg_status_vm = Reg(resetVal = Bool(false)); @@ -142,8 +140,7 @@ class rocketDpathPCR extends Component cnt = cnt + reg_vecbank(i) io.vecbankcnt := cnt(3,0) - io.vec_eaddr := reg_vec_eaddr - io.vec_xcpt := reg_vec_xcpt + io.vechold := reg_vechold val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0)) when (io.badvaddr_wen) { @@ -174,6 +171,7 @@ class rocketDpathPCR extends Component when (io.eret) { reg_status_s := reg_status_ps; reg_status_et := Bool(true); + reg_vechold := Bool(false) } when (reg_count === reg_compare) { @@ -211,8 +209,7 @@ class rocketDpathPCR extends Component when (waddr === PCR_K1) { reg_k1 := wdata; } when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; } when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) } - when (waddr === PCR_VEC_EADDR) { reg_vec_eaddr := wdata(VADDR_BITS,0) } - when (waddr === PCR_VEC_XCPT) { reg_vec_xcpt := wdata(2,0) } + when (waddr === PCR_VEC_HOLD) { reg_vechold := reg_status_ev && wdata(0) } } rdata := Bits(0, 64) diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 86334e29..1ef4dd92 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -12,8 +12,8 @@ class ioDpathVecInterface extends Bundle val vximm1q_bits = Bits(SZ_VIMM, OUTPUT) val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT) val vcntq_bits = Bits(SZ_VLEN, OUTPUT) - val eaddr = Bits(64, OUTPUT) - val exception = Bool(OUTPUT) + val backup = Bool(OUTPUT) + val backup_addr = Bits(64, OUTPUT) val kill = Bool(OUTPUT) val hold = Bool(OUTPUT) } @@ -30,8 +30,8 @@ class ioDpathVec extends Bundle val vecbankcnt = UFix(4, INPUT) val wdata = Bits(64, INPUT) val rs2 = Bits(64, INPUT) - val vec_eaddr = Bits(64, INPUT) - val vec_xcpt = Bits(3, INPUT) + val vechold = Bool(INPUT) + val pcrw = new ioWritePort() val wen = Bool(OUTPUT) val appvl = UFix(12, OUTPUT) } @@ -137,10 +137,10 @@ class rocketDpathVec extends Component io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0) - io.iface.eaddr := io.vec_eaddr - io.iface.exception := io.vec_xcpt(0) - io.iface.kill := io.vec_xcpt(1) - io.iface.hold := io.vec_xcpt(2) + io.iface.backup := io.pcrw.en && (io.pcrw.addr === PCR_VEC_BACKUP) + io.iface.backup_addr := io.pcrw.data + io.iface.kill := io.pcrw.en && (io.pcrw.addr === PCR_VEC_KILL) + io.iface.hold := io.vechold io.ctrl.valid := io.valid io.ctrl.inst := io.inst