riscv/rocket-chip
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Get in line with FIRRTL randomization flag changes (#231)

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Howard Mao 2016-08-29 12:29:01 -07:00 committed by Andrew Waterman
parent 35948918b6
commit a19bd6de96
2 changed files with 5 additions and 2 deletions
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2
firrtl

@ -1 +1 @@
Subproject commit 197760a962633d0e6140bcff16b96cc3d6b4e776 Subproject commit a2af16c1fb1f5166eab34188df9944012da3cbc3

5
vsim/Makefrag
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@ -48,7 +48,10 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \ +define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \ +define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE \ +define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+libext+.v \ +libext+.v \
VCS_OPTS += +vpi VCS_OPTS += +vpi