riscv/rocket-chip
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Don't route branch comparison result through ALU output mux

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This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
This commit is contained in:
Andrew Waterman
2017-10-07 17:31:23 -07:00
parent 36c39d01e4
commit a0e5a20b60
2 changed files with 7 additions and 6 deletions
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3
src/main/scala/rocket/RocketCore.scala
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@ -152,6 +152,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val mem_reg_raw_inst = Reg(UInt())
val mem_reg_wdata = Reg(Bits())
val mem_reg_rs2 = Reg(Bits())
val mem_br_taken = Reg(Bool())
val take_pc_mem = Wire(Bool())
val wb_reg_valid = Reg(Bool())
@ -361,7 +362,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
// memory stage
val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
val mem_br_taken = mem_reg_wdata(0)
val mem_br_target = mem_reg_pc.asSInt +
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
@ -403,6 +403,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
mem_reg_raw_inst := ex_reg_raw_inst
mem_reg_pc := ex_reg_pc
mem_reg_wdata := alu.io.out
mem_br_taken := alu.io.cmp_out
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
val typ = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_ctrl.mem_type)