From a0dcd42e800941d371bcc6062f012003f49db8d3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Sep 2016 17:48:59 -0700 Subject: [PATCH] avoid erroneously setting tags valid during flush --- src/main/scala/rocket/dcache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/dcache.scala b/src/main/scala/rocket/dcache.scala index 68dab522..5f313f74 100644 --- a/src/main/scala/rocket/dcache.scala +++ b/src/main/scala/rocket/dcache.scala @@ -239,7 +239,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_update_meta) || (s2_victimize && !s2_victim_dirty) metaWriteArb.io.in(0).bits.way_en := s2_victim_way metaWriteArb.io.in(0).bits.idx := s2_req.addr(idxMSB, idxLSB) - metaWriteArb.io.in(0).bits.data.coh := Mux(s2_hit, s2_new_hit_state, ClientMetadata.onReset) + metaWriteArb.io.in(0).bits.data.coh := Mux(s2_valid_hit, s2_new_hit_state, ClientMetadata.onReset) metaWriteArb.io.in(0).bits.data.tag := s2_req.addr(paddrBits-1, untagBits) // acquire @@ -345,7 +345,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { val newCoh = Wire(init = probeNewCoh) releaseWay := s2_probe_way when (s2_victimize && s2_victim_dirty) { - assert(!s2_hit_state.isValid()) + assert(!(s2_valid && s2_hit_state.isValid())) release_state := s_voluntary_writeback probe_bits.addr_block := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) }