diff --git a/riscv-rocket b/riscv-rocket
index 76cb0d00..8b3c51e6 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit 76cb0d00d540d5336dd9871bb7556fc1b42a4d85
+Subproject commit 8b3c51e6e8203b507c8782ab660d96ee91da9280
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 3976c2c5..5b98c41c 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -223,21 +223,21 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
   //val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
   val mem_serdes = new MemSerdes(htif_width)
 
-  val hub = new CoherenceHubBroadcast()(chWithHtifConf)
+  //val hub = new CoherenceHubBroadcast()(chWithHtifConf)
   //val adapter = new CoherenceHubAdapter()(lnWithHtifConf)
-  //val hub = new L2CoherenceAgent()(chWithHtifConf)
-  //val net = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf)
+  val hub = new L2CoherenceAgent()(chWithHtifConf)
+  val net = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf)
   //net.io(0) <> adapter.io.net
   //hub.io.tiles <> adapter.io.hub
-  //hub.io.network <> net.io(0)
+  hub.io.network <> net.io(0)
 
   for (i <- 1 to conf.ln.nTiles) {
-    //net.io(i) <> io.tiles(i-1)
-    hub.io.tiles(i-1) <> io.tiles(i-1)
+    net.io(i) <> io.tiles(i-1)
+    //hub.io.tiles(i-1) <> io.tiles(i-1)
     hub.io.incoherent(i-1) := io.incoherent(i-1)
   }
-  //net.io(conf.ln.nTiles+1) <> io.htif
-  hub.io.tiles(conf.ln.nTiles) <> io.htif
+  net.io(conf.ln.nTiles+1) <> io.htif
+  //hub.io.tiles(conf.ln.nTiles) <> io.htif
   hub.io.incoherent(conf.ln.nTiles) := Bool(true)
 
   llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
diff --git a/uncore b/uncore
index bf8c0b24..29e55842 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit bf8c0b248a0ba912aeda50102f28927aec0d5e08
+Subproject commit 29e55842f7bd5c119dcac85fbc935fc2c24487b2