Merge pull request #849 from freechipsproject/l2-tlb
L1 memory system improvements
This commit is contained in:
Andrew Waterman
GitHub
commit
a0cbc376b4
@ -146,6 +146,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
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tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)
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tlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
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tlb.io.req.bits.sfence.bits.addr := s1_req.addr
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tlb.io.req.bits.passthrough := s1_req.phys
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tlb.io.req.bits.vaddr := s1_req.addr
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tlb.io.req.bits.instruction := false
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@ -473,7 +474,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
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}
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when (s2_probe) {
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s1_nack := true
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val probeNack = Wire(init = true.B)
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when (s2_meta_error) {
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release_state := s_probe_retry
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}.elsewhen (s2_prb_ack_data) {
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@ -484,9 +485,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
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}.otherwise {
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tl_out.c.valid := true
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s1_nack := !releaseDone
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probeNack := !releaseDone
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release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
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}
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when (probeNack) { s1_nack := true }
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}
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when (release_state === s_probe_retry) {
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metaArb.io.in(6).valid := true
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@ -168,12 +168,13 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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fq.io.enq.bits.pc := s2_pc
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io.cpu.npc := ~(~Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) | (coreInstBytes-1)) // discard LSB(s)
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fq.io.enq.bits.data := icache.io.resp.bits
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fq.io.enq.bits.data := icache.io.resp.bits.data
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.xcpt := s2_tlb_resp
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fq.io.enq.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb.valid := s2_btb_resp_valid
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fq.io.enq.bits.btb.bits := s2_btb_resp_bits
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fq.io.enq.bits.xcpt := s2_tlb_resp
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when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true }
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io.cpu.resp <> fq.io.deq
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@ -58,6 +58,13 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
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}
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}
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class ICacheResp(outer: ICache) extends Bundle {
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val data = UInt(width = outer.icacheParams.fetchBytes*8)
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val ae = Bool()
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override def cloneType = new ICacheResp(outer).asInstanceOf[this.type]
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}
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val hartid = UInt(INPUT, hartIdLen)
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val req = Decoupled(new ICacheReq).flip
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@ -66,7 +73,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val resp = Valid(UInt(width = outer.icacheParams.fetchBytes*8))
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val resp = Valid(new ICacheResp(outer))
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val invalidate = Bool(INPUT)
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val tl_out = outer.masterNode.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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@ -145,15 +152,18 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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v
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}
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = tECC.width(tagBits))))
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val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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val accruedRefillError = Reg(Bool())
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val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError)
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when (refill_done) {
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val tag = tECC.encode(refill_tag)
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tag_array.write(refill_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
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val enc_tag = tECC.encode(Cat(refillError, refill_tag))
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tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (tl_out.d.fire()) {
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accruedRefillError := refillError
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// clear bit when refill starts so hit-under-miss doesn't fetch bad data
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
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}
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@ -164,6 +174,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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}
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val s1_tag_disparity = Wire(Vec(nWays, Bool()))
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val s1_tl_error = Wire(Vec(nWays, Bool()))
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val wordBits = outer.icacheParams.fetchBytes*8
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val s1_dout = Wire(Vec(nWays, UInt(width = dECC.width(wordBits))))
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@ -179,8 +190,12 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i,
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addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i)
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val s1_vb = vb_array(Cat(UInt(i), s1_idx)) && !s1_slaveValid
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s1_tag_disparity(i) := s1_vb && tECC.decode(tag_rdata(i)).error
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s1_tag_hit(i) := scratchpadHit || (s1_vb && tECC.decode(tag_rdata(i)).uncorrected === s1_tag)
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val enc_tag = tECC.decode(tag_rdata(i))
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val (tl_error, tag) = Split(enc_tag.uncorrected, tagBits)
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val tagMatch = s1_vb && tag === s1_tag
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s1_tag_disparity(i) := s1_vb && enc_tag.error
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s1_tl_error(i) := tagMatch && tl_error.toBool
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s1_tag_hit(i) := tagMatch || scratchpadHit
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}
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assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
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@ -212,7 +227,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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require(tECC.isInstanceOf[uncore.util.IdentityCode])
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require(dECC.isInstanceOf[uncore.util.IdentityCode])
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require(outer.icacheParams.itimAddr.isEmpty)
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io.resp.bits := Mux1H(s1_tag_hit, s1_dout)
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io.resp.bits.data := Mux1H(s1_tag_hit, s1_dout)
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io.resp.bits.ae := s1_tl_error.asUInt.orR
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io.resp.valid := s1_valid && s1_hit
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case 2 =>
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@ -221,11 +237,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid || s1_slaveValid).asUInt.orR
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val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_valid || s1_slaveValid)
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val s2_data_decoded = dECC.decode(s2_way_mux)
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val s2_disparity = s2_tag_disparity || s2_data_decoded.error
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when (s2_valid && s2_disparity) { invalidate := true }
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io.resp.bits := s2_data_decoded.uncorrected
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io.resp.bits.data := s2_data_decoded.uncorrected
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io.resp.bits.ae := s2_tl_error
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io.resp.valid := s2_valid && s2_hit && !s2_disparity
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tl_in.map { tl =>
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@ -708,6 +708,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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dtlb.io.req.bits.sfence.valid := s1_sfence
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dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
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dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)
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dtlb.io.req.bits.sfence.bits.addr := s1_req.addr
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dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
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dtlb.io.req.bits.passthrough := s1_req.phys
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dtlb.io.req.bits.vaddr := s1_req.addr
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@ -11,6 +11,7 @@ import coreplex.CacheBlockBytes
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import uncore.constants._
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import uncore.tilelink2._
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import util._
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import uncore.util.ParityCode
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import scala.collection.mutable.ListBuffer
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@ -37,7 +38,7 @@ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
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class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
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with HasRocketCoreParameters {
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val ptbr = new PTBR().asInput
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val invalidate = Bool(INPUT)
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val sfence = Valid(new SFenceReq).flip
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val status = new MStatus().asInput
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val pmp = Vec(nPMPs, new PMP).asInput
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}
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@ -125,17 +126,69 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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data(r) := pte.ppn
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}
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when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
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when (io.dpath.invalidate) { valid := 0 }
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when (io.dpath.sfence.valid && !io.dpath.sfence.bits.rs1) { valid := 0 }
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(hit && count < pgLevels-1, Mux1H(hits, data))
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}
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io.mem.req.valid := state === s_req
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val l2_refill = RegNext(false.B)
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val (l2_hit, l2_pte) = if (coreParams.nL2TLBEntries == 0) (false.B, Wire(new PTE)) else {
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class Entry extends Bundle {
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val ppn = UInt(width = ppnBits)
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val d = Bool()
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val a = Bool()
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val u = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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}
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val code = new ParityCode
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require(isPow2(coreParams.nL2TLBEntries))
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val idxBits = log2Ceil(coreParams.nL2TLBEntries)
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val tagBits = vpnBits - idxBits
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val ram = SeqMem(coreParams.nL2TLBEntries, UInt(width = code.width(new Entry().getWidth + tagBits)))
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val g = Reg(UInt(width = coreParams.nL2TLBEntries))
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val valid = RegInit(UInt(0, coreParams.nL2TLBEntries))
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val (r_tag, r_idx) = Split(r_req.addr, idxBits)
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when (l2_refill) {
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val entry = Wire(new Entry)
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entry := r_pte
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ram.write(r_idx, code.encode(Cat(entry.asUInt, r_tag)))
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val mask = UIntToOH(r_idx)
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valid := valid | mask
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g := Mux(r_pte.g, g | mask, g & ~mask)
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}
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when (io.dpath.sfence.valid) {
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valid :=
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Mux(io.dpath.sfence.bits.rs1, valid & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
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Mux(io.dpath.sfence.bits.rs2, valid & g, 0.U))
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}
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val s0_valid = !l2_refill && arb.io.out.fire()
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val s1_valid = RegNext(s0_valid)
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val s2_valid = RegNext(s1_valid && valid(r_idx))
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val s1_rdata = ram.read(arb.io.out.bits.addr(idxBits-1, 0), s0_valid)
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val s2_rdata = code.decode(RegEnable(s1_rdata, s1_valid))
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when (s2_valid && s2_rdata.error) { valid := 0.U }
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val (s2_entry, s2_tag) = Split(s2_rdata.uncorrected, tagBits)
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val s2_hit = s2_valid && !s2_rdata.error && r_tag === s2_tag
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val s2_pte = Wire(new PTE)
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s2_pte := s2_entry.asTypeOf(new Entry)
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s2_pte.g := g(r_idx)
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s2_pte.v := true
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(s2_hit, s2_pte)
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}
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io.mem.req.valid := state === s_req && !l2_hit
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := M_XRD
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io.mem.req.bits.typ := log2Ceil(xLen/8)
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io.mem.req.bits.addr := pte_addr
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io.mem.s1_kill := s1_kill
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io.mem.s1_kill := s1_kill || l2_hit
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io.mem.invalidate_lr := Bool(false)
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val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
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@ -159,7 +212,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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// control state machine
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switch (state) {
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is (s_ready) {
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when (arb.io.out.valid) {
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when (arb.io.out.fire()) {
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state := s_req
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}
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count := UInt(0)
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@ -186,6 +239,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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state := s_req
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count := count + 1
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}.otherwise {
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l2_refill := pte.v && !invalid_paddr && count === pgLevels-1
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resp_ae := pte.v && invalid_paddr
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state := s_ready
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resp_valid(r_req_dest) := true
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@ -198,6 +252,12 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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}
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}
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}
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when (l2_hit) {
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state := s_ready
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resp_valid(r_req_dest) := true
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resp_ae := false
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r_pte := l2_pte
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}
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}
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/** Mix-ins for constructing tiles that might have a PTW */
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@ -25,6 +25,7 @@ case class RocketCoreParams(
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nPMPs: Int = 8,
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nPerfCounters: Int = 0,
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nCustomMRWCSRs: Int = 0,
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nL2TLBEntries: Int = 0,
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mtvecInit: Option[BigInt] = Some(BigInt(0)),
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mtvecWritable: Boolean = true,
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fastLoadWord: Boolean = true,
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@ -588,8 +589,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
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io.imem.sfence.bits.rs1 := wb_ctrl.mem_type(0)
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io.imem.sfence.bits.rs2 := wb_ctrl.mem_type(1)
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io.imem.sfence.bits.addr := wb_reg_wdata
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io.imem.sfence.bits.asid := wb_reg_rs2
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io.ptw.invalidate := io.imem.sfence.valid && !io.imem.sfence.bits.rs1
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io.ptw.sfence := io.imem.sfence
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ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt
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@ -20,6 +20,7 @@ case object ASIdBits extends Field[Int]
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class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
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val rs1 = Bool()
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val rs2 = Bool()
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val addr = UInt(width = vaddrBits)
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val asid = UInt(width = asIdBits max 1) // TODO zero-width
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}
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@ -252,6 +253,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
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}
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when (sfence) {
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assert((io.req.bits.sfence.bits.addr >> pgIdxBits) === vpn(vpnBits-1,0))
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valid := Mux(io.req.bits.sfence.bits.rs1, valid & ~hits(totalEntries-1, 0),
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Mux(io.req.bits.sfence.bits.rs2, valid & entries.map(_.g).asUInt, 0))
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}
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@ -24,6 +24,7 @@ trait CoreParams {
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val retireWidth: Int
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val instBits: Int
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val nLocalInterrupts: Int
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val nL2TLBEntries: Int
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}
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trait HasCoreParameters extends HasTileParameters {
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