riscv/rocket-chip
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Start adding RoCC

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This commit is contained in:
Andrew Waterman
2013-09-14 15:31:50 -07:00
parent d053bdc89f
commit a0cb711451
4 changed files with 114 additions and 27 deletions
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20
rocket/src/main/scala/core.scala
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@ -10,6 +10,7 @@ class RocketIO(implicit conf: RocketConfiguration) extends Bundle
val imem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)
val ptw = new DatapathPTWIO().flip
val rocc = new RoCCInterface().flip
}
class Core(implicit conf: RocketConfiguration) extends Module
@ -19,6 +20,15 @@ class Core(implicit conf: RocketConfiguration) extends Module
val ctrl = Module(new Control)
val dpath = Module(new Datapath)
val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(4,6))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor?
fpu.io.dfma.valid := Bool(false)
fpu
} else null
ctrl.io.dpath <> dpath.io.ctrl
dpath.io.host <> io.host
@ -30,12 +40,6 @@ class Core(implicit conf: RocketConfiguration) extends Module
dpath.io.ptw <> io.ptw
val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(4,6))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor?
fpu.io.dfma.valid := Bool(false)
fpu
} else null
ctrl.io.rocc <> io.rocc
dpath.io.rocc <> io.rocc
}