riscv/rocket-chip
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Revert to old AUIPC definition

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This commit is contained in:
Andrew Waterman 2014-02-10 19:04:42 -08:00
parent 1456170c6d
commit a09ff9fdc7
3 changed files with 5 additions and 10 deletions
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3
rocket/src/main/scala/consts.scala
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@ -23,8 +23,7 @@ trait ScalarOpConstants {
val A1_X = Bits("b??", 2) val A1_X = Bits("b??", 2)
val A1_ZERO = UInt(0, 2) val A1_ZERO = UInt(0, 2)
val A1_RS1 = UInt(1, 2) val A1_RS1 = UInt(1, 2)
val A1_PCHI = UInt(2, 2) val A1_PC = UInt(2, 2)
val A1_PC = UInt(3, 2)
val IMM_X = Bits("b???", 3) val IMM_X = Bits("b???", 3)
val IMM_S = UInt(0, 3) val IMM_S = UInt(0, 3)

2
rocket/src/main/scala/ctrl.scala
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@ -99,7 +99,7 @@ object XDecode extends DecodeConstants
JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), JAL-> List(Y, N,N,BR_J, N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), JALR-> List(Y, N,N,BR_N, Y,N,Y,A2_FOUR,A1_PC, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PCHI,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N),

10
rocket/src/main/scala/dpath.scala
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@ -132,13 +132,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val ex_rs = for (i <- 0 until id_rs.size) val ex_rs = for (i <- 0 until id_rs.size)
yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst) val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst)
val ex_op1_hi = MuxLookup(ex_reg_sel_alu1, ex_reg_pc.toSInt >> 12, Seq( val ex_op1 = MuxLookup(ex_reg_sel_alu1, SInt(0), Seq(
A1_RS1 -> (ex_rs(0).toSInt >> 12), A1_RS1 -> ex_rs(0).toSInt,
A1_ZERO -> SInt(0))) A1_PC -> ex_reg_pc.toSInt))
val ex_op1_lo = MuxLookup(ex_reg_sel_alu1, UInt(0), Seq(
A1_RS1 -> ex_rs(0)(11,0),
A1_PC -> ex_reg_pc(11,0)))
val ex_op1 = Cat(ex_op1_hi, ex_op1_lo)
val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq( val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq(
A2_RS2 -> ex_rs(1).toSInt, A2_RS2 -> ex_rs(1).toSInt,
A2_IMM -> ex_imm, A2_IMM -> ex_imm,