riscv/rocket-chip
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The FPGA doesn't have an HTIF clock divider

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We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.
This commit is contained in:
Palmer Dabbelt 2016-02-22 15:30:19 -08:00
parent c1b5f71ee7
commit a073c37e36
1 changed files with 4 additions and 0 deletions
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csrc/htif_emulator.h
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@ -24,7 +24,11 @@ class htif_emulator_t : public htif_pthread_t
void set_clock_divisor(int divisor, int hold_cycles) void set_clock_divisor(int divisor, int hold_cycles)
{ {
#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR
/* We only want to write the HTIF clock divisor SCR on targets where it
* actually exists (there isn't one on the FPGA, for example). */
write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16); write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR, divisor | hold_cycles << 16);
#endif
} }
void start() void start()