riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: fix typo (#1104)

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-11-10 15:11:56 -08:00 committed by GitHub
parent 35d377d122
commit a061b16ee3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/Configs.scala
View File

@ -248,7 +248,7 @@ class WithSynchronousRocketTiles extends Config((site, here, up) => {
}
})
class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
class WithAsynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
r.copy(crossingType = AsynchronousCrossing(depth, sync))
}