riscv/rocket-chip
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Default TLB size = 32

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@davidbiancolin
This commit is contained in:
Andrew Waterman 2017-03-20 01:29:26 -07:00
parent 1875407316
commit a03556220c
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/HellaCache.scala
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@ -19,7 +19,7 @@ case class DCacheParams(
nSets: Int = 64, nSets: Int = 64,
nWays: Int = 4, nWays: Int = 4,
rowBits: Int = 64, rowBits: Int = 64,
nTLBEntries: Int = 8, nTLBEntries: Int = 32,
splitMetadata: Boolean = false, splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,
nMSHRs: Int = 1, nMSHRs: Int = 1,

2
src/main/scala/rocket/ICache.scala
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@ -16,7 +16,7 @@ case class ICacheParams(
nSets: Int = 64, nSets: Int = 64,
nWays: Int = 4, nWays: Int = 4,
rowBits: Int = 128, rowBits: Int = 128,
nTLBEntries: Int = 8, nTLBEntries: Int = 32,
cacheIdBits: Int = 0, cacheIdBits: Int = 0,
splitMetadata: Boolean = false, splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,