riscv/rocket-chip
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make PutBlock wmask argument match Put

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This commit is contained in:
Howard Mao 2016-06-28 13:09:20 -07:00
parent b936aa9826
commit 9feca99d5d
4 changed files with 7 additions and 23 deletions
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2
uncore/src/main/scala/converters/Nasti.scala
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@ -319,7 +319,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
addr_block = nasti_addr_block(aw_req), addr_block = nasti_addr_block(aw_req),
addr_beat = put_count, addr_beat = put_count,
data = io.nasti.w.bits.data, data = io.nasti.w.bits.data,
wmask = io.nasti.w.bits.strb), wmask = Some(io.nasti.w.bits.strb)),
Put( Put(
client_xact_id = aw_req.id, client_xact_id = aw_req.id,
addr_block = nasti_addr_block(aw_req), addr_block = nasti_addr_block(aw_req),

7
uncore/src/main/scala/converters/Tilelink.scala
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@ -107,8 +107,7 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
client_xact_id = irel.client_xact_id, client_xact_id = irel.client_xact_id,
addr_block = irel.addr_block, addr_block = irel.addr_block,
addr_beat = irel.addr_beat, addr_beat = irel.addr_beat,
data = irel.data, data = irel.data)
wmask = Acquire.fullWriteMask)
io.in.release.ready := rel_helper.fire(io.in.release.valid) io.in.release.ready := rel_helper.fire(io.in.release.valid)
io.out.acquire <> acqArb.io.out io.out.acquire <> acqArb.io.out
@ -264,7 +263,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
addr_block = put_block, addr_block = put_block,
addr_beat = put_beat, addr_beat = put_beat,
data = put_data.toBits, data = put_data.toBits,
wmask = put_wmask.toBits) wmask = Some(put_wmask.toBits))
io.out.acquire.valid := sending_put || (!shrink && io.in.acquire.valid) io.out.acquire.valid := sending_put || (!shrink && io.in.acquire.valid)
io.out.acquire.bits := MuxCase(get_block_acquire, Seq( io.out.acquire.bits := MuxCase(get_block_acquire, Seq(
@ -444,7 +443,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
Cat(acq_addr_beat, oacq_ctr.value) Cat(acq_addr_beat, oacq_ctr.value)
else acq_addr_beat, else acq_addr_beat,
data = acq_data_buffer(outerDataBits - 1, 0), data = acq_data_buffer(outerDataBits - 1, 0),
wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig) wmask = Some(acq_wmask_buffer(outerWriteMaskBits - 1, 0)))(outerConfig)
val get_acquire = Get( val get_acquire = Get(
client_xact_id = iacq.client_xact_id, client_xact_id = iacq.client_xact_id,

2
uncore/src/main/scala/devices/Dma.scala
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@ -354,7 +354,7 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
addr_block = dst_block, addr_block = dst_block,
addr_beat = put_beat, addr_beat = put_beat,
data = put_data, data = put_data,
wmask = put_mask) wmask = Some(put_mask))
val get_acquire = GetBlock( val get_acquire = GetBlock(
client_xact_id = get_half, client_xact_id = get_half,

19
uncore/src/main/scala/tilelink/Definitions.scala
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@ -585,22 +585,7 @@ object PutBlock {
addr_block: UInt, addr_block: UInt,
addr_beat: UInt, addr_beat: UInt,
data: UInt, data: UInt,
wmask: UInt) wmask: Option[UInt] = None,
(implicit p: Parameters): Acquire = {
BuiltInAcquireBuilder(
a_type = Acquire.putBlockType,
client_xact_id = client_xact_id,
addr_block = addr_block,
addr_beat = addr_beat,
data = data,
wmask = wmask,
alloc = Bool(true))
}
def apply(
client_xact_id: UInt,
addr_block: UInt,
addr_beat: UInt,
data: UInt,
alloc: Bool = Bool(true)) alloc: Bool = Bool(true))
(implicit p: Parameters): Acquire = { (implicit p: Parameters): Acquire = {
BuiltInAcquireBuilder( BuiltInAcquireBuilder(
@ -609,7 +594,7 @@ object PutBlock {
addr_block = addr_block, addr_block = addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
data = data, data = data,
wmask = Acquire.fullWriteMask, wmask = wmask.getOrElse(Acquire.fullWriteMask),
alloc = alloc) alloc = alloc)
} }
} }