riscv/rocket-chip
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Add RV32F support

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This commit is contained in:
Andrew Waterman
2016-09-06 23:53:12 -07:00
parent 66e9f027e0
commit 9fea4c83da
8 changed files with 337 additions and 235 deletions
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8
src/main/scala/rocket/csr.scala
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@ -260,11 +260,13 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val cpu_ren = io.rw.cmd =/= CSR.N && !system_insn
val cpu_wen = cpu_ren && io.rw.cmd =/= CSR.R
val isa_string = "IM" +
val isa_string = "I" +
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (usingFPU) "F" else "") +
(if (usingFPU && xLen > 32) "D" else "") +
(if (usingVM) "S" else "") +
(if (usingUser) "U" else "") +
(if (usingAtomics) "A" else "") +
(if (usingFPU) "FD" else "") +
(if (usingRoCC) "X" else "")
val isa = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) |
isa_string.map(x => 1 << (x - 'A')).reduce(_|_)