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tilelink: BusBypass can be sent to DeadlockDevice

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This commit is contained in:
Henry Cook 2017-10-11 12:45:36 -07:00
parent ec056535dc
commit 9f8e3d8879
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/devices/tilelink/BusBypass.scala
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@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import scala.math.min import scala.math.min
abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends LazyModule abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false)(implicit p: Parameters) extends LazyModule
{ {
protected val nodeIn = TLIdentityNode() protected val nodeIn = TLIdentityNode()
protected val nodeOut = TLIdentityNode() protected val nodeOut = TLIdentityNode()
@ -18,7 +18,8 @@ abstract class TLBusBypassBase(beatBytes: Int)(implicit p: Parameters) extends L
protected val bar = LazyModule(new TLBusBypassBar) protected val bar = LazyModule(new TLBusBypassBar)
protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
protected val error = LazyModule(new TLError(ErrorParams(everything), beatBytes)) protected val error = if (deadlock) LazyModule(new DeadlockDevice(ErrorParams(everything), beatBytes))
else LazyModule(new TLError(ErrorParams(everything), beatBytes))
// order matters // order matters
bar.node := nodeIn bar.node := nodeIn