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Add PLIC covers (#1229)

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* Add another FPU hazard cover

* Add some PLIC covers
This commit is contained in:
Andrew Waterman 2018-02-06 17:33:33 -08:00 committed by GitHub
parent 36cba65e60
commit 9f6d586e8c
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2 changed files with 22 additions and 0 deletions
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21
src/main/scala/devices/tilelink/Plic.scala
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@ -12,6 +12,8 @@ import freechips.rocketchip.tile.XLen
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
import scala.math.min
class GatewayPLICIO extends Bundle {
@ -231,6 +233,25 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
pending(0) := false
for (e <- enables)
e(0) := false
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0
val completed = completer(0)
cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
cover((diff & (diff - 1)) =/= 0, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (UInt(1) << priority(0).getWidth) && maxDevs(0) <= Cat(UInt(1), threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}

1
src/main/scala/tile/FPU.scala
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@ -823,6 +823,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
io.sboard_set := wb_reg_valid && !wb_cp_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2))))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5, 6) || io.inst(14,12) === 7 && io.fcsr_rm >= 5