Add PLIC covers (#1229)
* Add another FPU hazard cover * Add some PLIC covers
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@ -12,6 +12,8 @@ import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.SourceInfo
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import scala.math.min
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import scala.math.min
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class GatewayPLICIO extends Bundle {
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class GatewayPLICIO extends Bundle {
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@ -231,6 +233,25 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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pending(0) := false
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pending(0) := false
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for (e <- enables)
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for (e <- enables)
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e(0) := false
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e(0) := false
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if (nDevices >= 2) {
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val claimed = claimer(0) && maxDevs(0) > 0
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val completed = completer(0)
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cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
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cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
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val ep = enables(0).asUInt & pending.asUInt
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val ep2 = RegNext(ep)
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val diff = ep & ~ep2
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cover((diff & (diff - 1)) =/= 0, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
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if (nPriorities > 0)
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ccover(maxDevs(0) > (UInt(1) << priority(0).getWidth) && maxDevs(0) <= Cat(UInt(1), threshold(0)),
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"THRESHOLD", "interrupt pending but less than threshold")
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}
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
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}
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}
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}
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}
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@ -823,6 +823,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
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io.sboard_set := wb_reg_valid && !wb_cp_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt)
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io.sboard_set := wb_reg_valid && !wb_cp_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt)
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io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2))))
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io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2))))
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io.sboard_clra := waddr
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io.sboard_clra := waddr
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ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
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// we don't currently support round-max-magnitude (rm=4)
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// we don't currently support round-max-magnitude (rm=4)
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io.illegal_rm := io.inst(14,12).isOneOf(5, 6) || io.inst(14,12) === 7 && io.fcsr_rm >= 5
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io.illegal_rm := io.inst(14,12).isOneOf(5, 6) || io.inst(14,12) === 7 && io.fcsr_rm >= 5
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