tilelink2: Fragmenter needs to update subaddress
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@ -167,7 +167,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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// Swallow up non-data ack fragments
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// Swallow up non-data ack fragments
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val drop = (out.d.bits.opcode === TLMessages.AccessAck) && (dFragnum =/= UInt(0))
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val drop = (out.d.bits.opcode === TLMessages.AccessAck) && (dFragnum =/= UInt(0))
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out.d.ready := in.d.ready || drop
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out.d.ready := in.d.ready || drop
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in.d.valid := out.d.valid && drop
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in.d.valid := out.d.valid && !drop
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in.d.bits := out.d.bits // pass most stuff unchanged
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in.d.bits := out.d.bits // pass most stuff unchanged
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in.d.bits.source := out.d.bits.source >> fragmentBits
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in.d.bits.source := out.d.bits.source >> fragmentBits
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in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
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in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
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@ -220,12 +220,13 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
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val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
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val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
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val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
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when (out.d.fire()) { gennum := new_gennum }
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when (out.a.fire()) { gennum := new_gennum }
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val delay = !aHasData && aFragnum =/= UInt(0)
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val delay = !aHasData && aFragnum =/= UInt(0)
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out.a.valid := in.a.valid
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready && !delay
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in.a.ready := out.a.ready && !delay
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out.a.bits := in.a.bits
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out.a.bits := in.a.bits
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out.a.bits.address := in.a.bits.address | (~aFragnum << log2Ceil(minSize) & aOrigOH1)
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out.a.bits.source := Cat(in.a.bits.source, aFragnum)
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out.a.bits.source := Cat(in.a.bits.source, aFragnum)
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out.a.bits.size := aFrag
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out.a.bits.size := aFrag
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