riscv/rocket-chip
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Fix D$ arbiter for >2 inputs

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This commit is contained in:
Andrew Waterman
2014-03-04 16:32:17 -08:00
parent fa75f6e81e
commit 9f2e16c58a
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/arbiter.scala
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@@ -46,7 +46,7 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu
resp.bits.replay := io.mem.resp.bits.replay && tag_hit
io.requestor(i).replay_next.valid := io.mem.replay_next.valid &&
io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(log2Up(n))
io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(i)
io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
}
}