riscv/rocket-chip
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make sure access to invalid physical address treated as exception

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This commit is contained in:
Howard Mao committed 2015-09-22 10:11:43 -07:00
1 parent 16c748576a
commit 9eb988a4c6
4 files changed
+17 -9
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rocket/src/main/scala/nbdcache.scala
+2 -3
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@@ -32,7 +32,6 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
val sdqDepth = params(StoreDataQueueDepth)
val nMSHRs = params(NMSHRs)
val nIOMSHRs = params(NIOMSHRs)
val mmioBase = params(MMIOBase)
}
abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
@@ -788,8 +787,8 @@ class HellaCache extends L1HellaCacheModule {
io.cpu.xcpt.ma.ld := s1_read && misaligned
io.cpu.xcpt.ma.st := s1_write && misaligned
io.cpu.xcpt.pf.ld := !s1_req.phys && s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := !s1_req.phys && s1_write && dtlb.io.resp.xcpt_st
io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
assert (!(Reg(next=
(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&